#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: D:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764-AITHAS #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\msgmii_clkrst.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\msgmii_cnvrxi.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\msgmii_cnvrxo.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\msgmii_cnvtxi.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\msgmii_cnvtxo.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\peanx_sync.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\msgmii_peanx_top.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\r10b8b.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\perex_pcs.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\perex_pma.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\petbm.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\petcr.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\t8b10b.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\petex_top.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\msgmii_tbi.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\msgmii_core.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\rx4096x36.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\amcxfif_clkrst.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\amcxfif_hst.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\amcxrfif_fab.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\amcxrfif_sys.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\amcxtfif_fab.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\amcxtfif_sys.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\amcxtfif_wtm.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\amcxfif.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\arfque.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\decoder.v" @I:"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\decoder.v":"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\include.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\dmarx.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\dmatx.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\dma_dual.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\slave.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\tsm_sysreg.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\mahbe_dual.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\mmcxwol.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pecrc.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\perfn_top.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\permc_top.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\petfn_top.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\petmc_top.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pe_mcxmac_core.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pecar.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pehst.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemgt.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pe_mcxmac.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemstat_cntrl.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemstat_eim.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemstat_ladd.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemstat_linc.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemstat_sadd.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemstat_sinc.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemstat_sinchd.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemstat_sincnf.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemstat_store.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\pemstat.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\sib_fifo_mem2p.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\sib_sync_2flp.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\sib_fifo_top.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\ptp_hstinf.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\ptp_rfp.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\ptp_rtc.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\ptp_tfp.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\ptp_top.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\si_sal.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\sib_sync_pulse.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\tsmac_top.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\tx2048x40.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CORETSE_AHB\2.1.105\rtl\vlog\core_obfuscated\CoreTSE_top.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver\CORETSE_AHB_0\rtl\vlog\core_obfuscated\CoreTSE_AHB.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver\FCCC_0\CoreTSE_Webserver_FCCC_0_FCCC.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver\FCCC_1\CoreTSE_Webserver_FCCC_1_FCCC.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver\FCCC_2\CoreTSE_Webserver_FCCC_2_FCCC.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver\FCCC_3\CoreTSE_Webserver_FCCC_3_FCCC.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver_MSS\CoreTSE_Webserver_MSS_syn.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver_MSS\CoreTSE_Webserver_MSS.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver\OSC_0\CoreTSE_Webserver_OSC_0_OSC.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver\SERDES_IF2_0\CoreTSE_Webserver_SERDES_IF2_0_SERDES_IF2_syn.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver\SERDES_IF2_0\CoreTSE_Webserver_SERDES_IF2_0_SERDES_IF2.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" @I::"D:\CASES\coretse\CoreTSE_Webserver\component\work\CoreTSE_Webserver\CoreTSE_Webserver.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module CoreTSE_Webserver @N:CG364 : smartfusion2.v(126) | Synthesizing module AND2 @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF @W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000001000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z1 @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000001000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_8_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000100 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z2 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000100 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_4_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z3 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z4 @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M0_AHBSLOTENABLE=17'b00000000000001000 M1_AHBSLOTENABLE=17'b00000000000000100 M2_AHBSLOTENABLE=17'b00000000000000100 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_0_8_4_4_0_0s @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite FAMILY=6'b010011 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b1 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b0 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b1 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b1 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b00000000000001000 M1_AHBSLOTENABLE=17'b00000000000000100 M2_AHBSLOTENABLE=17'b00000000000000100 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000000000000 Generated name = CoreAHBLite_Z5 @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000001 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z6 @W:CL113 : coreconfigp.v(626) | Feedback mux created for signal soft_reset_reg[16:0]. @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization. @W:CL250 : coreconfigp.v(626) | All reachable assignments to soft_reset_reg[16:0] assign 0, register removed by optimization @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z7 @W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base @N:CG364 : dmatx.v(6) | Synthesizing module dmatx CORETSE_AHBoOI=32'b00000000000000000000000000000000 Generated name = dmatx_0s @N:CG179 : dmatx.v(1168) | Removing redundant assignment @N:CG179 : dmatx.v(1176) | Removing redundant assignment @N:CG179 : dmatx.v(1184) | Removing redundant assignment @N:CG364 : dmarx.v(6) | Synthesizing module dmarx CORETSE_AHBoOI=32'b00000000000000000000000000000000 Generated name = dmarx_0s @N:CG179 : dmarx.v(1097) | Removing redundant assignment @N:CG179 : dmarx.v(1105) | Removing redundant assignment @N:CG179 : dmarx.v(1113) | Removing redundant assignment @W:CG133 : dmarx.v(297) | No assignment to CORETSE_AHBoOol @N:CG364 : dma_dual.v(6) | Synthesizing module dma_dual CORETSE_AHBoOI=32'b00000000000000000000000000000000 CORETSE_AHBOII=32'b00000000000000000000000000000000 Generated name = dma_dual_0s_0s @N:CG179 : dma_dual.v(917) | Removing redundant assignment @N:CG179 : dma_dual.v(973) | Removing redundant assignment @W:CG360 : dma_dual.v(392) | No assignment to wire CORETSE_AHBiO0l @W:CG360 : dma_dual.v(395) | No assignment to wire CORETSE_AHBOI0l @W:CG360 : dma_dual.v(419) | No assignment to wire CORETSE_AHBOl0l @W:CG360 : dma_dual.v(421) | No assignment to wire CORETSE_AHBIl0l @W:CG360 : dma_dual.v(560) | No assignment to wire CORETSE_AHBoi0l @W:CG133 : dma_dual.v(568) | No assignment to CORETSE_AHBii0l @W:CG360 : dma_dual.v(576) | No assignment to wire CORETSE_AHBOO1l @W:CG133 : dma_dual.v(584) | No assignment to CORETSE_AHBIO1l @W:CL265 : dma_dual.v(1507) | Pruning bit 5 of CORETSE_AHBl00l[9:0] -- not in use ... @W:CL265 : dma_dual.v(1507) | Pruning bit 2 of CORETSE_AHBl00l[9:0] -- not in use ... @N:CG364 : slave.v(6) | Synthesizing module slave @N:CG364 : decoder.v(6) | Synthesizing module decoder @N:CG364 : tsm_sysreg.v(4) | Synthesizing module tsm_sysreg CORETSE_AHBOII=32'b00000000000000000000000000000000 CORETSE_AHBoOI=32'b00000000000000000000000000000000 Generated name = tsm_sysreg_0s_0s @W:CG360 : tsm_sysreg.v(211) | No assignment to wire CORETSE_AHBiO1oI @W:CG360 : tsm_sysreg.v(214) | No assignment to wire CORETSE_AHBOI1oI @W:CG360 : tsm_sysreg.v(222) | No assignment to wire CORETSE_AHBoi0l @W:CG133 : tsm_sysreg.v(230) | No assignment to CORETSE_AHBii0l @W:CG360 : tsm_sysreg.v(238) | No assignment to wire CORETSE_AHBOO1l @W:CG133 : tsm_sysreg.v(246) | No assignment to CORETSE_AHBIO1l @N:CG364 : mahbe_dual.v(5) | Synthesizing module mahbe_dual CORETSE_AHBoOI=32'b00000000000000000000000000000000 CORETSE_AHBOII=32'b00000000000000000000000000000000 Generated name = mahbe_dual_0s_0s @N:CG364 : arfque.v(6) | Synthesizing module arfque @N:CG364 : amcxtfif_fab.v(6) | Synthesizing module amcxtfif_fab TABITS=32'b00000000000000000000000000001011 CORETSE_AHBIo1=32'b00000000000000000000000000100000 CORETSE_AHBlo1=32'b00000000000000000000000000000010 CORETSE_AHBoloI=11'b00000000000 CORETSE_AHBol0I=12'b000000000000 CORETSE_AHBIoII=32'b00000000000000000000000000000001 Generated name = amcxtfif_fab_11s_32s_2s_0_0_1s @N:CG364 : amcxtfif_sys.v(6) | Synthesizing module amcxtfif_sys TABITS=32'b00000000000000000000000000001011 CORETSE_AHBIo1=32'b00000000000000000000000000100000 CORETSE_AHBlo1=32'b00000000000000000000000000000010 CORETSE_AHBoOI=32'b00000000000000000000000000000000 CORETSE_AHBol0I=12'b000000000000 CORETSE_AHBiOiI=14'b00000000000000 CORETSE_AHBIoII=32'b00000000000000000000000000000001 Generated name = amcxtfif_sys_11s_32s_2s_0s_0_0_1s @W:CL271 : amcxtfif_sys.v(1656) | Pruning bits 1 to 0 of CORETSE_AHBl0iI[13:0] -- not in use ... @W:CL271 : amcxtfif_sys.v(1475) | Pruning bits 13 to 2 of CORETSE_AHBo0iI[13:0] -- not in use ... @W:CL271 : amcxtfif_sys.v(1447) | Pruning bits 1 to 0 of CORETSE_AHBI0iI[13:0] -- not in use ... @W:CL271 : amcxtfif_sys.v(1380) | Pruning bits 1 to 0 of CORETSE_AHBO0iI[13:0] -- not in use ... @W:CL265 : amcxtfif_sys.v(1609) | Pruning bit 38 of CORETSE_AHBI1iI[39:0] -- not in use ... @N:CG364 : amcxrfif_fab.v(6) | Synthesizing module amcxrfif_fab RABITS=32'b00000000000000000000000000001100 CORETSE_AHBIo1=32'b00000000000000000000000000100000 CORETSE_AHBlo1=32'b00000000000000000000000000000010 CORETSE_AHBol0I=13'b0000000000000 CORETSE_AHBIoII=32'b00000000000000000000000000000001 Generated name = amcxrfif_fab_12s_32s_2s_0_1s @N:CG179 : amcxrfif_fab.v(971) | Removing redundant assignment @N:CG179 : amcxrfif_fab.v(977) | Removing redundant assignment @N:CG179 : amcxrfif_fab.v(983) | Removing redundant assignment @N:CG179 : amcxrfif_fab.v(989) | Removing redundant assignment @N:CG179 : amcxrfif_fab.v(995) | Removing redundant assignment @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSE_AHBI0OI[36] to a constant 0 @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSE_AHBI0OI[37] to a constant 0 @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSE_AHBI0OI[38] to a constant 0 @W:CL190 : amcxrfif_fab.v(1581) | Optimizing register bit CORETSE_AHBI0OI[39] to a constant 0 @W:CL279 : amcxrfif_fab.v(1581) | Pruning register bits 39 to 36 of CORETSE_AHBI0OI[39:0] @W:CL169 : amcxrfif_fab.v(1022) | Pruning register CORETSE_AHBO10I @N:CG364 : amcxrfif_sys.v(6) | Synthesizing module amcxrfif_sys CORETSE_AHBoOI=32'b00000000000000000000000000000000 RABITS=32'b00000000000000000000000000001100 CORETSE_AHBIo1=32'b00000000000000000000000000100000 CORETSE_AHBlo1=32'b00000000000000000000000000000010 CORETSE_AHBlO1I=14'b00000000000000 CORETSE_AHBoO1I=13'b0000000000000 CORETSE_AHBol0I=15'b000000000000000 CORETSE_AHBIoII=32'b00000000000000000000000000000001 Generated name = amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s @N:CG364 : amcxtfif_wtm.v(6) | Synthesizing module amcxtfif_wtm RABITS=32'b00000000000000000000000000001100 CORETSE_AHBIoII=32'b00000000000000000000000000000001 CORETSE_AHBoloI=12'b000000000000 CORETSE_AHBol0I=13'b0000000000000 Generated name = amcxtfif_wtm_12s_1s_0_0 @N:CG364 : amcxfif_hst.v(6) | Synthesizing module amcxfif_hst TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 CORETSE_AHBIo1=32'b00000000000000000000000000100000 CORETSE_AHBlo1=32'b00000000000000000000000000000010 CORETSE_AHBIoII=32'b00000000000000000000000000000001 CORETSE_AHBlOlI=13'b0000000000000 CORETSE_AHBoOlI=4'b0000 CORETSE_AHBiOlI=19'b0000000000000000000 CORETSE_AHBOIlI=12'b111111111111 CORETSE_AHBIIlI=12'b111111111111 CORETSE_AHBlIlI=14'b00000000000000 CORETSE_AHBoIlI=4'b0000 CORETSE_AHBiIlI=3'b000 CORETSE_AHBOllI=18'b000000000000000000 CORETSE_AHBIllI=13'b1111111111111 CORETSE_AHBlllI=13'b1111111111111 CORETSE_AHBollI=12'b111111111111 Generated name = amcxfif_hst_Z8 @W:CG360 : amcxfif_hst.v(904) | No assignment to wire CORETSE_AHBIolI @N:CG364 : amcxfif_clkrst.v(7) | Synthesizing module amcxfif_clkrst @N:CG364 : amcxfif.v(6) | Synthesizing module amcxfif TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 CORETSE_AHBIo1=32'b00000000000000000000000000100000 CORETSE_AHBlo1=32'b00000000000000000000000000000010 CORETSE_AHBoOI=32'b00000000000000000000000000000000 Generated name = amcxfif_11s_12s_32s_2s_0s @N:CG364 : petmc_top.v(6) | Synthesizing module petmc_top @N:CG364 : pecrc.v(6) | Synthesizing module pecrc @N:CG364 : petfn_top.v(6) | Synthesizing module petfn_top CORETSE_AHBiOI=32'b00000000000000000000000000000000 CORETSE_AHBlOI=1'b0 CORETSE_AHBIoII=32'b00000000000000000000000000000001 Generated name = petfn_top_0s_0_1s @N:CG179 : petfn_top.v(9927) | Removing redundant assignment @N:CG179 : petfn_top.v(9987) | Removing redundant assignment @W:CG133 : petfn_top.v(418) | No assignment to CORETSE_AHBOo1II @W:CG360 : petfn_top.v(421) | No assignment to wire CORETSE_AHBIo1II @W:CG360 : petfn_top.v(445) | No assignment to wire CORETSE_AHBOilII @W:CG360 : petfn_top.v(956) | No assignment to wire CORETSE_AHBlOIlI @W:CL169 : petfn_top.v(4062) | Pruning register CORETSE_AHBIioII[15:0] @W:CL190 : petfn_top.v(3748) | Optimizing register bit CORETSE_AHBOiiII[5] to a constant 0 @W:CL190 : petfn_top.v(3748) | Optimizing register bit CORETSE_AHBOiiII[6] to a constant 0 @W:CL279 : petfn_top.v(3748) | Pruning register bits 6 to 5 of CORETSE_AHBOiiII[6:0] @N:CG364 : perfn_top.v(6) | Synthesizing module perfn_top CORETSE_AHBoOI=32'b00000000000000000000000000000000 CORETSE_AHBlOI=1'b0 CORETSE_AHBIoII=32'b00000000000000000000000000000001 Generated name = perfn_top_0s_0_1s @W:CG360 : perfn_top.v(343) | No assignment to wire CORETSE_AHBo0lOI @W:CG360 : perfn_top.v(650) | No assignment to wire CORETSE_AHBIOoOI @W:CG133 : perfn_top.v(653) | No assignment to CORETSE_AHBlOoOI @N:CG364 : permc_top.v(6) | Synthesizing module permc_top @N:CG364 : pe_mcxmac_core.v(6) | Synthesizing module pe_mcxmac_core CORETSE_AHBlOI=1'b0 CORETSE_AHBoOI=32'b00000000000000000000000000000000 CORETSE_AHBiOI=32'b00000000000000000000000000000000 Generated name = pe_mcxmac_core_0_0s_0s @N:CG364 : pemgt.v(6) | Synthesizing module pemgt @N:CG364 : pehst.v(6) | Synthesizing module pehst @W:CG133 : pehst.v(613) | No assignment to CORETSE_AHBoiOo @W:CG133 : pehst.v(709) | No assignment to CORETSE_AHBiiOo @W:CG133 : pehst.v(714) | No assignment to CORETSE_AHBOOIo @W:CG133 : pehst.v(716) | No assignment to CORETSE_AHBIOIo @W:CL169 : pehst.v(1969) | Pruning register CORETSE_AHBo1oo @W:CL169 : pehst.v(1939) | Pruning register CORETSE_AHBl1oo @W:CL169 : pehst.v(1909) | Pruning register CORETSE_AHBI1oo @N:CG364 : pecar.v(6) | Synthesizing module pecar @N:CG364 : pe_mcxmac.v(6) | Synthesizing module pe_mcxmac CORETSE_AHBlOI=1'b0 CORETSE_AHBiOI=32'b00000000000000000000000000000000 CORETSE_AHBoOI=32'b00000000000000000000000000000000 Generated name = pe_mcxmac_0_0s_0s @W:CG360 : pe_mcxmac.v(676) | No assignment to wire CORETSE_AHBOOi1 @W:CG360 : pe_mcxmac.v(679) | No assignment to wire CORETSE_AHBo1O1 @W:CG360 : pe_mcxmac.v(682) | No assignment to wire CORETSE_AHBi1O1 @N:CG364 : tsmac_top.v(4) | Synthesizing module tsmac_top TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 MCXMAC_SAL_ON=32'b00000000000000000000000000000001 MCXMAC_WOL_ON=32'b00000000000000000000000000000001 MCXMAC_STATS_ON=32'b00000000000000000000000000000001 CORETSE_AHBoOI=32'b00000000000000000000000000000000 CORETSE_AHBiOI=32'b00000000000000000000000000000000 CORETSE_AHBlOI=32'b00000000000000000000000000000000 CORETSE_AHBIII=32'b00000000000000000000000000000001 CORETSE_AHBlII=32'b00000000000000000000000000000010 CORETSE_AHBoII=32'b00000000000000000000000000000001 CORETSE_AHBiII=32'b00000000000000000000000000000010 CORETSE_AHBOlI=32'b00000000000000000000000000010010 CORETSE_AHBIlI=32'b00000000000000000000000000010010 CORETSE_AHBllI=32'b00000000000000000000000000000101 CORETSE_AHBolI=32'b00000000000000000000000000000101 CORETSE_AHBOII=32'b00000000000000000000000000000000 Generated name = tsmac_top_Z9 @N:CG364 : sib_sync_pulse.v(5) | Synthesizing module sib_sync_pulse @N:CG364 : sib_sync_2flp.v(5) | Synthesizing module sib_sync_2flp CORETSE_AHBlIloI=32'b00000000000000000000000000000001 CORETSE_AHBoIloI=32'b00000000000000000000000000000000 Generated name = sib_sync_2flp_1s_0s @W:CG133 : sib_sync_2flp.v(62) | No assignment to CORETSE_AHBOloI @N:CG364 : pemstat_cntrl.v(6) | Synthesizing module pemstat_cntrl @W:CG360 : pemstat_cntrl.v(108) | No assignment to wire CORETSE_AHBi1li @W:CG360 : pemstat_cntrl.v(110) | No assignment to wire CORETSE_AHBOoli @W:CG133 : pemstat_cntrl.v(113) | No assignment to CORETSE_AHBIoli @W:CG133 : pemstat_cntrl.v(115) | No assignment to CORETSE_AHBloli @W:CG133 : pemstat_cntrl.v(124) | No assignment to CORETSE_AHBOOoI @W:CG133 : pemstat_cntrl.v(126) | No assignment to CORETSE_AHBIili @N:CG364 : pemstat_linc.v(6) | Synthesizing module pemstat_linc @N:CG179 : pemstat_linc.v(183) | Removing redundant assignment @N:CG179 : pemstat_linc.v(255) | Removing redundant assignment @N:CG364 : pemstat_ladd.v(6) | Synthesizing module pemstat_ladd @N:CG179 : pemstat_ladd.v(338) | Removing redundant assignment @N:CG364 : pemstat_sinc.v(6) | Synthesizing module pemstat_sinc @N:CG179 : pemstat_sinc.v(183) | Removing redundant assignment @N:CG179 : pemstat_sinc.v(255) | Removing redundant assignment @N:CG364 : pemstat_sinchd.v(6) | Synthesizing module pemstat_sinchd @N:CG179 : pemstat_sinchd.v(183) | Removing redundant assignment @N:CG179 : pemstat_sinchd.v(255) | Removing redundant assignment @N:CG364 : pemstat_sadd.v(6) | Synthesizing module pemstat_sadd @N:CG179 : pemstat_sadd.v(201) | Removing redundant assignment @N:CG179 : pemstat_sadd.v(278) | Removing redundant assignment @N:CG364 : pemstat_sincnf.v(6) | Synthesizing module pemstat_sincnf @N:CG179 : pemstat_sincnf.v(183) | Removing redundant assignment @N:CG179 : pemstat_sincnf.v(255) | Removing redundant assignment @N:CG364 : pemstat_store.v(6) | Synthesizing module pemstat_store @N:CG364 : pemstat_eim.v(6) | Synthesizing module pemstat_eim @N:CG364 : pemstat.v(6) | Synthesizing module pemstat @N:CG364 : mmcxwol.v(6) | Synthesizing module mmcxwol @N:CG364 : si_sal.v(4) | Synthesizing module si_sal @N:CG179 : si_sal.v(886) | Removing redundant assignment @W:CG360 : tsmac_top.v(277) | No assignment to wire CORETSE_AHBll0 @W:CG360 : tsmac_top.v(279) | No assignment to wire CORETSE_AHBol0 @W:CG360 : tsmac_top.v(281) | No assignment to wire CORETSE_AHBil0 @W:CG360 : tsmac_top.v(283) | No assignment to wire CORETSE_AHBO00 @W:CG360 : tsmac_top.v(285) | No assignment to wire CORETSE_AHBI00 @N:CG364 : tx2048x40.v(6) | Synthesizing module tx2048x40 TABITS=32'b00000000000000000000000000001011 CORETSE_AHBIoII=32'b00000000000000000000000000000001 CORETSE_AHBOoOoI=32'b00000000000000000000000000000001 CORETSE_AHBIoOoI=32'b00000000000000000000000000000100 Generated name = tx2048x40_11s_1s_1s_4s @N:CL134 : tx2048x40.v(131) | Found RAM CORETSE_AHBooOoI, depth=2048, width=40 @N:CG364 : rx4096x36.v(6) | Synthesizing module rx4096x36 RABITS=32'b00000000000000000000000000001100 CORETSE_AHBIoII=32'b00000000000000000000000000000001 CORETSE_AHBOoOoI=32'b00000000000000000000000000000001 CORETSE_AHBIoOoI=32'b00000000000000000000000000000100 Generated name = rx4096x36_12s_1s_1s_4s @N:CL134 : rx4096x36.v(131) | Found RAM CORETSE_AHBooOoI, depth=4096, width=36 @N:CG364 : CoreTSE_top.v(2) | Synthesizing module CoreTSE_top FAMILY=32'b00000000000000000000000000010011 GMII_TBI=32'b00000000000000000000000000000001 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 MCXMAC_SAL_ON=32'b00000000000000000000000000000001 MCXMAC_WOL_ON=32'b00000000000000000000000000000001 MCXMAC_STATS_ON=32'b00000000000000000000000000000001 MDIO_PHYID=32'b00000000000000000000000000010010 Generated name = CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s @N:CG364 : msgmii_clkrst.v(7) | Synthesizing module msgmii_clkrst @N:CG364 : msgmii_cnvtxi.v(6) | Synthesizing module msgmii_cnvtxi @W:CL169 : msgmii_cnvtxi.v(319) | Pruning register CORETSE_AHBiio0[3:0] @N:CG364 : msgmii_cnvtxo.v(6) | Synthesizing module msgmii_cnvtxo @N:CG364 : t8b10b.v(6) | Synthesizing module t8b10b @N:CG364 : petex_top.v(6) | Synthesizing module petex_top CORETSE_AHBlOI=32'b00000000000000000000000000000000 CORETSE_AHBIoII=32'b00000000000000000000000000000001 Generated name = petex_top_0s_1s @N:CG179 : petex_top.v(2036) | Removing redundant assignment @W:CL169 : petex_top.v(639) | Pruning register CORETSE_AHBIllII @N:CG364 : perex_pma.v(6) | Synthesizing module perex_pma @W:CL169 : perex_pma.v(1536) | Pruning register CORETSE_AHBOOlOI @W:CL169 : perex_pma.v(1506) | Pruning register CORETSE_AHBiiIOI @W:CL169 : perex_pma.v(1476) | Pruning register CORETSE_AHBoiIOI @N:CG364 : r10b8b.v(6) | Synthesizing module r10b8b @N:CG364 : perex_pcs.v(6) | Synthesizing module perex_pcs CORETSE_AHBlOI=32'b00000000000000000000000000000000 CORETSE_AHBIoII=32'b00000000000000000000000000000001 Generated name = perex_pcs_0s_1s @W:CL169 : perex_pcs.v(4065) | Pruning register CORETSE_AHBiIIOI @W:CL169 : perex_pcs.v(4010) | Pruning register CORETSE_AHBlIIOI @W:CL169 : perex_pcs.v(3869) | Pruning register CORETSE_AHBlOIOI @W:CL265 : perex_pcs.v(1203) | Pruning bit 3 of CORETSE_AHBi0oi[3:0] -- not in use ... @W:CL265 : perex_pcs.v(1203) | Pruning bit 1 of CORETSE_AHBi0oi[3:0] -- not in use ... @N:CL177 : perex_pcs.v(3570) | Sharing sequential element CORETSE_AHBIiOOI. @N:CG364 : peanx_sync.v(6) | Synthesizing module peanx_sync @N:CG364 : msgmii_peanx_top.v(6) | Synthesizing module msgmii_peanx_top @W:CL169 : msgmii_peanx_top.v(3007) | Pruning register CORETSE_AHBiI01 @W:CL265 : msgmii_peanx_top.v(2929) | Pruning bit 14 of CORETSE_AHBlI01[15:0] -- not in use ... @W:CL265 : msgmii_peanx_top.v(2329) | Pruning bit 14 of CORETSE_AHBl1l1[15:0] -- not in use ... @N:CL177 : msgmii_peanx_top.v(2255) | Sharing sequential element CORETSE_AHBI0l1. @N:CG364 : petbm.v(6) | Synthesizing module petbm CORETSE_AHBlOI=32'b00000000000000000000000000000000 CORETSE_AHBIoII=32'b00000000000000000000000000000001 Generated name = petbm_0s_1s @W:CL169 : petbm.v(2461) | Pruning register CORETSE_AHBloIII @N:CG364 : petcr.v(7) | Synthesizing module petcr @N:CL177 : petcr.v(329) | Sharing sequential element CORETSE_AHBOI0o. @N:CL177 : petcr.v(470) | Sharing sequential element CORETSE_AHBOIlII. @N:CG364 : msgmii_tbi.v(6) | Synthesizing module msgmii_tbi CORETSE_AHBlOI=32'b00000000000000000000000000000000 CORETSE_AHBIoII=32'b00000000000000000000000000000001 Generated name = msgmii_tbi_0s_1s @W:CG360 : msgmii_tbi.v(387) | No assignment to wire CORETSE_AHBo101 @N:CG364 : msgmii_cnvrxi.v(6) | Synthesizing module msgmii_cnvrxi @W:CL169 : msgmii_cnvrxi.v(416) | Pruning register CORETSE_AHBli10[1:0] @N:CG364 : msgmii_cnvrxo.v(6) | Synthesizing module msgmii_cnvrxo @N:CG364 : msgmii_core.v(6) | Synthesizing module msgmii_core CORETSE_AHBlOI=32'b00000000000000000000000000000000 MDIO_PHYID=32'b00000000000000000000000000010010 Generated name = msgmii_core_0s_18s @W:CG781 : CoreTSE_top.v(1323) | Undriven input CORETSE_AHBlI0 on instance CORETSE_AHBilI, tying to 0 @W:CG781 : CoreTSE_top.v(1327) | Undriven input CORETSE_AHBoI0 on instance CORETSE_AHBilI, tying to 0 @W:CG781 : CoreTSE_top.v(1331) | Undriven input CORETSE_AHBiI0 on instance CORETSE_AHBilI, tying to 0 @W:CG781 : CoreTSE_top.v(1335) | Undriven input CORETSE_AHBOl0 on instance CORETSE_AHBilI, tying to 0 @W:CG781 : CoreTSE_top.v(1339) | Undriven input CORETSE_AHBIl0 on instance CORETSE_AHBilI, tying to 0 @W:CG360 : CoreTSE_top.v(589) | No assignment to wire CORETSE_AHBo0 @W:CG360 : CoreTSE_top.v(697) | No assignment to wire CORETSE_AHBOOI @N:CG364 : CoreTSE_AHB.v(2) | Synthesizing module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB FAMILY=32'b00000000000000000000000000010011 GMII_TBI=32'b00000000000000000000000000000001 PACKET_SIZE=32'b00000000000000000000000000001011 SAL=32'b00000000000000000000000000000001 WOL=32'b00000000000000000000000000000001 STATS=32'b00000000000000000000000000000001 MDIO_PHYID=32'b00000000000000000000000000010010 Generated name = CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s @W:CG781 : CoreTSE_AHB.v(668) | Undriven input AHBS_HPROT_I on instance CoreTSE_top_inst, tying to 0 @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF @N:CG364 : CoreTSE_Webserver_MSS_syn.v(5) | Synthesizing module MSS_075 @N:CG364 : CoreTSE_Webserver_MSS.v(9) | Synthesizing module CoreTSE_Webserver_MSS @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC @N:CG364 : smartfusion2.v(372) | Synthesizing module GND @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC @N:CG364 : CoreTSE_Webserver_FCCC_0_FCCC.v(5) | Synthesizing module CoreTSE_Webserver_FCCC_0_FCCC @N:CG364 : CoreTSE_Webserver_FCCC_1_FCCC.v(5) | Synthesizing module CoreTSE_Webserver_FCCC_1_FCCC @N:CG364 : CoreTSE_Webserver_FCCC_2_FCCC.v(5) | Synthesizing module CoreTSE_Webserver_FCCC_2_FCCC @N:CG364 : CoreTSE_Webserver_FCCC_3_FCCC.v(5) | Synthesizing module CoreTSE_Webserver_FCCC_3_FCCC @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : CoreTSE_Webserver_OSC_0_OSC.v(5) | Synthesizing module CoreTSE_Webserver_OSC_0_OSC @N:CG364 : smartfusion2.v(320) | Synthesizing module INBUF_DIFF @N:CG364 : CoreTSE_Webserver_SERDES_IF2_0_SERDES_IF2_syn.v(5) | Synthesizing module SERDESIF_075 @N:CG364 : CoreTSE_Webserver_SERDES_IF2_0_SERDES_IF2.v(5) | Synthesizing module CoreTSE_Webserver_SERDES_IF2_0_SERDES_IF2 @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET @N:CG364 : CoreTSE_Webserver.v(9) | Synthesizing module CoreTSE_Webserver @W:CL157 : CoreTSE_Webserver_OSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : CoreTSE_Webserver_OSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : CoreTSE_Webserver_OSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : CoreTSE_Webserver_OSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : CoreTSE_Webserver_OSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : CoreTSE_Webserver_OSC_0_OSC.v(14) | Input XTL is unused @W:CL247 : CoreTSE_Webserver_MSS.v(79) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused @W:CL246 : CoreTSE_AHB.v(275) | Input port bits 2 to 1 of HSIZE[2:0] are unused @W:CL246 : CoreTSE_AHB.v(283) | Input port bits 2 to 1 of HBURST[2:0] are unused @W:CL157 : CoreTSE_AHB.v(344) | *Output TXHLOCK has undriven bits -- simulation mismatch possible. @W:CL157 : CoreTSE_AHB.v(415) | *Output RXHLOCK has undriven bits -- simulation mismatch possible. @N:CL177 : petcr.v(343) | Sharing sequential element CORETSE_AHBII0o. @N:CL177 : petcr.v(484) | Sharing sequential element CORETSE_AHBIIlII. @W:CL190 : petbm.v(669) | Optimizing register bit CORETSE_AHBl0OII[5] to a constant 0 @W:CL260 : petbm.v(669) | Pruning register bit 5 of CORETSE_AHBl0OII[5:0] @N:CL201 : msgmii_peanx_top.v(3325) | Trying to extract state machine for register CORETSE_AHBil01 @W:CL247 : msgmii_peanx_top.v(113) | Input port bit 14 of CORETSE_AHBolO1[15:0] is unused @W:CL247 : msgmii_peanx_top.v(113) | Input port bit 11 of CORETSE_AHBolO1[15:0] is unused @N:CL201 : perex_pcs.v(4633) | Trying to extract state machine for register CORETSE_AHBIii0 Extracted state machine for register CORETSE_AHBIii0 State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : CoreTSE_top.v(276) | Input port bits 31 to 10 of AHBS_HADDR_I[31:0] are unused @W:CL246 : CoreTSE_top.v(276) | Input port bits 1 to 0 of AHBS_HADDR_I[31:0] are unused @W:CL157 : CoreTSE_top.v(228) | *Output TSMAC_TXD_O has undriven bits -- simulation mismatch possible. @W:CL157 : CoreTSE_top.v(231) | *Output TSMAC_TXEN_O has undriven bits -- simulation mismatch possible. @W:CL157 : CoreTSE_top.v(234) | *Output TSMAC_TXER_O has undriven bits -- simulation mismatch possible. @W:CL159 : CoreTSE_top.v(242) | Input TSMAC_RXD_I is unused @W:CL159 : CoreTSE_top.v(245) | Input TSMAC_RXDV_I is unused @W:CL159 : CoreTSE_top.v(248) | Input TSMAC_RXER_I is unused @W:CL159 : CoreTSE_top.v(251) | Input TSMAC_CRS_I is unused @W:CL159 : CoreTSE_top.v(254) | Input TSMAC_COL_I is unused @W:CL159 : CoreTSE_top.v(459) | Input AHBS_HBURST_I is unused @W:CL159 : CoreTSE_top.v(462) | Input AHBS_HMASTLOCK_I is unused @W:CL159 : CoreTSE_top.v(465) | Input AHBS_HPROT_I is unused @W:CL159 : CoreTSE_top.v(468) | Input AHBS_HSIZE_I is unused @W:CL246 : pemstat_eim.v(151) | Input port bits 24 to 20 of CORETSE_AHBOOIi[31:0] are unused @W:CL247 : pemstat_store.v(176) | Input port bit 31 of CORETSE_AHBl1li[31:0] is unused @W:CL246 : pemstat_sincnf.v(44) | Input port bits 30 to 12 of CORETSE_AHBl1li[30:0] are unused @W:CL246 : pemstat_sadd.v(54) | Input port bits 30 to 12 of CORETSE_AHBl1li[30:0] are unused @W:CL246 : pemstat_sinchd.v(44) | Input port bits 30 to 12 of CORETSE_AHBl1li[30:0] are unused @W:CL246 : pemstat_sinc.v(44) | Input port bits 30 to 12 of CORETSE_AHBl1li[30:0] are unused @W:CL246 : pemstat_ladd.v(54) | Input port bits 30 to 24 of CORETSE_AHBl1li[30:0] are unused @W:CL246 : pemstat_linc.v(44) | Input port bits 30 to 18 of CORETSE_AHBl1li[30:0] are unused @W:CL247 : pemstat_cntrl.v(51) | Input port bit 22 of CORETSE_AHBl1o[30:0] is unused @W:CL246 : pemstat_cntrl.v(51) | Input port bits 17 to 16 of CORETSE_AHBl1o[30:0] are unused @W:CL246 : pemstat_cntrl.v(62) | Input port bits 31 to 30 of CORETSE_AHBlOo1[51:0] are unused @W:CL246 : pemstat_cntrl.v(62) | Input port bits 23 to 21 of CORETSE_AHBlOo1[51:0] are unused @W:CL159 : sib_sync_2flp.v(24) | Input CORETSE_AHBllloI is unused @W:CL159 : sib_sync_2flp.v(26) | Input CORETSE_AHBolloI is unused @W:CL157 : tsmac_top.v(277) | *Output CORETSE_AHBll0 has undriven bits -- simulation mismatch possible. @W:CL157 : tsmac_top.v(279) | *Output CORETSE_AHBol0 has undriven bits -- simulation mismatch possible. @W:CL157 : tsmac_top.v(281) | *Output CORETSE_AHBil0 has undriven bits -- simulation mismatch possible. @W:CL157 : tsmac_top.v(283) | *Output CORETSE_AHBO00 has undriven bits -- simulation mismatch possible. @W:CL157 : tsmac_top.v(285) | *Output CORETSE_AHBI00 has undriven bits -- simulation mismatch possible. @W:CL159 : tsmac_top.v(267) | Input CORETSE_AHBOl0 is unused @W:CL159 : tsmac_top.v(269) | Input CORETSE_AHBIl0 is unused @W:CL159 : tsmac_top.v(271) | Input CORETSE_AHBlI0 is unused @W:CL159 : tsmac_top.v(273) | Input CORETSE_AHBoI0 is unused @W:CL159 : tsmac_top.v(275) | Input CORETSE_AHBiI0 is unused @W:CL159 : pecar.v(120) | Input CORETSE_AHBllo is unused @W:CL159 : pecar.v(130) | Input CORETSE_AHBl0o is unused @W:CL159 : pecar.v(143) | Input CORETSE_AHBOi1 is unused @A:CL153 : pehst.v(613) | *Unassigned bits of CORETSE_AHBoiOo are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(709) | *Unassigned bits of CORETSE_AHBiiOo are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(714) | *Unassigned bits of CORETSE_AHBOOIo are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(716) | *Unassigned bits of CORETSE_AHBIOIo are referenced and tied to 0 -- simulation mismatch possible. @W:CL159 : pehst.v(198) | Input CORETSE_AHBOi11 is unused @N:CL201 : pemgt.v(547) | Trying to extract state machine for register CORETSE_AHBiooo Extracted state machine for register CORETSE_AHBiooo State machine has 32 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 @W:CL247 : permc_top.v(98) | Input port bit 0 of CORETSE_AHBoo01[1:0] is unused @W:CL138 : perfn_top.v(3373) | Removing register 'CORETSE_AHBOIo1' because it is only assigned 0 or its original value. @N:CL201 : perfn_top.v(5127) | Trying to extract state machine for register CORETSE_AHBl1o @W:CL246 : perfn_top.v(142) | Input port bits 1 to 0 of CORETSE_AHBIii1[7:0] are unused @N:CL135 : petfn_top.v(6208) | Found seqShift CORETSE_AHBOlIlI, depth=3, width=8 @N:CL135 : petfn_top.v(7123) | Found seqShift CORETSE_AHBI0IlI, depth=4, width=1 @N:CL135 : petfn_top.v(6990) | Found seqShift CORETSE_AHBilIlI, depth=4, width=1 @N:CL135 : petfn_top.v(7241) | Found seqShift CORETSE_AHBo0IlI, depth=4, width=1 @N:CL135 : petfn_top.v(2644) | Found seqShift CORETSE_AHBlooII, depth=3, width=1 @N:CL135 : petfn_top.v(2813) | Found seqShift CORETSE_AHBOIiII, depth=3, width=4 @N:CL135 : petfn_top.v(8331) | Found seqShift CORETSE_AHBOl, depth=4, width=1 @N:CL135 : petfn_top.v(7636) | Found seqShift CORETSE_AHBoI, depth=4, width=1 @N:CL201 : petfn_top.v(10292) | Trying to extract state machine for register CORETSE_AHBlOo1 @W:CL246 : petfn_top.v(214) | Input port bits 1 to 0 of CORETSE_AHBI1i1[6:0] are unused @W:CL246 : petfn_top.v(216) | Input port bits 1 to 0 of CORETSE_AHBl1i1[6:0] are unused @W:CL246 : petfn_top.v(218) | Input port bits 1 to 0 of CORETSE_AHBo1i1[6:0] are unused @W:CL246 : petfn_top.v(226) | Input port bits 9 to 6 of CORETSE_AHBi1i1[9:0] are unused @W:CL159 : petfn_top.v(326) | Input CORETSE_AHBOoo1 is unused @W:CL159 : petfn_top.v(329) | Input CORETSE_AHBIoo1 is unused @W:CL159 : petfn_top.v(337) | Input CORETSE_AHBloo1 is unused @W:CL159 : petfn_top.v(340) | Input CORETSE_AHBooo1 is unused @W:CL159 : petfn_top.v(351) | Input CORETSE_AHBioo1 is unused @W:CL159 : petfn_top.v(343) | Input CORETSE_AHBOio1 is unused @W:CL247 : petmc_top.v(113) | Input port bit 0 of CORETSE_AHBoo01[1:0] is unused @W:CL159 : amcxfif_hst.v(232) | Input CORETSE_AHBO0OI is unused @N:CL201 : amcxtfif_wtm.v(268) | Trying to extract state machine for register CORETSE_AHBiOOl Extracted state machine for register CORETSE_AHBiOOl State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @W:CL246 : amcxrfif_sys.v(234) | Input port bits 39 to 36 of CORETSE_AHBIlII[39:0] are unused @N:CL135 : amcxrfif_fab.v(1079) | Found seqShift CORETSE_AHBOIOI, depth=3, width=1 @N:CL201 : amcxrfif_fab.v(588) | Trying to extract state machine for register CORETSE_AHBIi0I Extracted state machine for register CORETSE_AHBIi0I State machine has 5 reachable states with original encodings of: 0000 1000 1100 1110 1111 @W:CL247 : amcxrfif_fab.v(123) | Input port bit 12 of CORETSE_AHBllII[13:0] is unused @N:CL201 : amcxtfif_sys.v(804) | Trying to extract state machine for register CORETSE_AHBOIiI Extracted state machine for register CORETSE_AHBOIiI State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @W:CL247 : slave.v(74) | Input port bit 0 of HTRANS[1:0] is unused @W:CL159 : dma_dual.v(348) | Input CORETSE_AHBlIll is unused @W:CL159 : dma_dual.v(356) | Input CORETSE_AHBoIll is unused @N:CL201 : dmarx.v(1039) | Trying to extract state machine for register CORETSE_AHBI0ol Extracted state machine for register CORETSE_AHBI0ol State machine has 4 reachable states with original encodings of: 000 100 110 111 @N:CL201 : dmarx.v(501) | Trying to extract state machine for register CORETSE_AHBOOol Extracted state machine for register CORETSE_AHBOOol State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : dmarx.v(90) | Input port bits 1 to 0 of HRDATA[31:0] are unused @N:CL201 : dmatx.v(1110) | Trying to extract state machine for register CORETSE_AHBI0ol Extracted state machine for register CORETSE_AHBI0ol State machine has 4 reachable states with original encodings of: 000 100 110 111 @N:CL201 : dmatx.v(566) | Trying to extract state machine for register CORETSE_AHBOOol Extracted state machine for register CORETSE_AHBOOol State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @W:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused @W:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused @W:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused @W:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused @W:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused @W:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused @W:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused @W:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused @W:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused @W:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused @W:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused @W:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused @W:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused @W:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused @W:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused @W:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @W:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused @W:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused @W:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused @W:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused @W:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused @W:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused @W:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused @W:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(73) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(74) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(75) | Input HRESP_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(249) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_matrix4x16.v(250) | Input HREADYOUT_S16 is unused @W:CL159 : coreahblite_matrix4x16.v(251) | Input HRESP_S16 is unused @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @W:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 16 to 3 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 1 to 0 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 3 of SHRESP[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 1 to 0 of SHRESP[16:0] are unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 16 to 4 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 2 to 0 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 4 of SHRESP[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 2 to 0 of SHRESP[16:0] are unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused At c_ver Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 127MB peak: 151MB) Process took 0h:00m:08s realtime, 0h:00m:08s cputime # Thu Nov 17 15:26:43 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File D:\CASES\coretse\CoreTSE_Webserver_SC4.0\synthesis\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Nov 17 15:26:44 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:09s realtime, 0h:00m:09s cputime # Thu Nov 17 15:26:44 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File D:\CASES\coretse\CoreTSE_Webserver_SC4.0\synthesis\synwork\CoreTSE_Webserver_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 112MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Nov 17 15:26:46 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: D:\CASES\coretse\CoreTSE_Webserver\designer\CoreTSE_Webserver\synthesis.fdc Linked File: CoreTSE_Webserver_scck.rpt Printing clock summary report in "D:\CASES\coretse\CoreTSE_Webserver\synthesis\CoreTSE_Webserver_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 160MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 160MB) @W:BN231 : | Constraints on tristate nets currently not supported Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 160MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 160MB) @W:BN132 : coreahblite_matrix4x16.v(3626) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_16, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_15 @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_15, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_14 @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_14, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_13 @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_13, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_12 @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_12, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_11 @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_11, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_9, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_8, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_7, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance CoreAHBLite_0.matrix4x16.slavestage_6, because it is equivalent to instance CoreAHBLite_0.matrix4x16.slavestage_10 @N:BN362 : pemgt.v(2195) | Removing sequential instance CORETSE_AHBIiOo of view:PrimLib.dffr(prim) in hierarchy view:work.pemgt(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN362 : sib_sync_pulse.v(187) | Removing sequential instance CORETSE_AHBiO0oI\.CORETSE_AHBIO0oI of view:PrimLib.dffr(prim) in hierarchy view:work.sib_sync_pulse_1(verilog) because there are no references to its outputs @N:BN362 : sib_sync_pulse.v(187) | Removing sequential instance CORETSE_AHBiO0oI\.CORETSE_AHBIO0oI of view:PrimLib.dffr(prim) in hierarchy view:work.sib_sync_pulse_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_0_0s_0_1_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_2(verilog) because there are no references to its outputs @N:BN362 : pecar.v(630) | Removing sequential instance CORETSE_AHBlO0o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(683) | Removing sequential instance CORETSE_AHBII0o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1196) | Removing sequential instance CORETSE_AHBoO1o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1240) | Removing sequential instance CORETSE_AHBII1o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : msgmii_core.v(366) | Removing sequential instance CORETSE_AHBi11[9:0] of view:PrimLib.dffr(prim) in hierarchy view:work.msgmii_core_0s_18s(verilog) because there are no references to its outputs @N:BN362 : pemgt.v(2657) | Removing sequential instance CORETSE_AHBl1Oi of view:PrimLib.dffr(prim) in hierarchy view:work.pemgt(verilog) because there are no references to its outputs @N:BN362 : pecar.v(616) | Removing sequential instance CORETSE_AHBIO0o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(669) | Removing sequential instance CORETSE_AHBOI0o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1182) | Removing sequential instance CORETSE_AHBlO1o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1226) | Removing sequential instance CORETSE_AHBOI1o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(420) | Removing sequential instance CORETSE_AHBI1lo of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(471) | Removing sequential instance CORETSE_AHBOolo of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1055) | Removing sequential instance CORETSE_AHBoo0o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(250) | Removing sequential instance CORETSE_AHBol10 of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(289) | Removing sequential instance CORETSE_AHBO010 of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst(verilog) because there are no references to its outputs @N:BN362 : pecar.v(406) | Removing sequential instance CORETSE_AHBO1lo of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(457) | Removing sequential instance CORETSE_AHBi1lo of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1041) | Removing sequential instance CORETSE_AHBlo0o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1099) | Removing sequential instance CORETSE_AHBIi0o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1143) | Removing sequential instance CORETSE_AHBii0o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(237) | Removing sequential instance CORETSE_AHBll10 of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst(verilog) because there are no references to its outputs @N:BN362 : msgmii_clkrst.v(276) | Removing sequential instance CORETSE_AHBil10 of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_clkrst(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1085) | Removing sequential instance CORETSE_AHBOi0o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : pecar.v(1129) | Removing sequential instance CORETSE_AHBoi0o of view:PrimLib.dff(prim) in hierarchy view:work.pecar(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_0_8_0s_0_1_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog) because there are no references to its outputs @W:MT462 : coretse_webserver_serdes_if2_0_serdes_if2.v(98) | Net SERDES_IF2_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. syn_allowed_resources : blockrams=109 set on top level netlist CoreTSE_Webserver Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 190MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------- CLK1_PAD 50.0 MHz 20.000 declared default_clkgroup CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB 12.5 MHz 80.000 declared default_clkgroup FCCC_0/GL0 50.0 MHz 20.000 generated (from CLK1_PAD) default_clkgroup FCCC_1/GL0 62.5 MHz 16.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_1/GL1 62.5 MHz 16.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_2/GL0 125.0 MHz 8.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup FCCC_3/GL0 125.0 MHz 8.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup FCCC_3/GL1 125.0 MHz 8.000 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup OSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz 8.000 declared default_clkgroup SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 8.000 declared default_clkgroup System 100.0 MHz 10.000 system system_clkgroup pemgt|CORETSE_AHBi01_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 ========================================================================================================================================================== @W:MT532 : msgmii_clkrst.v(354) | Found signal identified as System clock which controls 3 sequential elements including CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBo1i0.CORETSE_AHBoO1. Using this clock, which has no specified timing constraint, can adversely impact design performance. @W:MT530 : pemgt.v(1863) | Found inferred clock pemgt|CORETSE_AHBi01_inferred_clock which controls 290 sequential elements including CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBooOo.CORETSE_AHBIIOi[7:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @W:MO111 : | Tristate driver CORETSE_AHB_0_AHBMTX_HLOCK_t on net CORETSE_AHB_0_AHBMTX_HLOCK has its enable tied to GND (module CoreTSE_Webserver) @W:MO111 : | Tristate driver CORETSE_AHB_0_AHBMRX_HLOCK_t on net CORETSE_AHB_0_AHBMRX_HLOCK has its enable tied to GND (module CoreTSE_Webserver) @N:BN225 : | Writing default property annotation file D:\CASES\coretse\CoreTSE_Webserver\synthesis\CoreTSE_Webserver.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 109MB peak: 190MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Thu Nov 17 15:26:49 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 164MB peak: 166MB) @W:BN231 : | Constraints on tristate nets currently not supported @W:MO111 : tsmac_top.v(285) | Tristate driver CORETSE_AHBI00 on net CORETSE_AHBI00 has its enable tied to GND (module tsmac_top_Z9) @W:MO111 : tsmac_top.v(283) | Tristate driver CORETSE_AHBO00 on net CORETSE_AHBO00 has its enable tied to GND (module tsmac_top_Z9) @W:MO111 : tsmac_top.v(281) | Tristate driver CORETSE_AHBil0 on net CORETSE_AHBil0 has its enable tied to GND (module tsmac_top_Z9) @W:MO111 : tsmac_top.v(279) | Tristate driver CORETSE_AHBol0 on net CORETSE_AHBol0 has its enable tied to GND (module tsmac_top_Z9) @W:MO111 : tsmac_top.v(277) | Tristate driver CORETSE_AHBll0 on net CORETSE_AHBll0 has its enable tied to GND (module tsmac_top_Z9) @W:MO111 : coretse_top.v(234) | Tristate driver TSMAC_TXER_O on net TSMAC_TXER_O has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(231) | Tristate driver TSMAC_TXEN_O on net TSMAC_TXEN_O has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(228) | Tristate driver TSMAC_TXD_O_1 on net TSMAC_TXD_O_1 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(228) | Tristate driver TSMAC_TXD_O_2 on net TSMAC_TXD_O_2 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(228) | Tristate driver TSMAC_TXD_O_3 on net TSMAC_TXD_O_3 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(228) | Tristate driver TSMAC_TXD_O_4 on net TSMAC_TXD_O_4 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(228) | Tristate driver TSMAC_TXD_O_5 on net TSMAC_TXD_O_5 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(228) | Tristate driver TSMAC_TXD_O_6 on net TSMAC_TXD_O_6 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(228) | Tristate driver TSMAC_TXD_O_7 on net TSMAC_TXD_O_7 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_top.v(228) | Tristate driver TSMAC_TXD_O_8 on net TSMAC_TXD_O_8 has its enable tied to GND (module CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s) @W:MO111 : coretse_ahb.v(415) | Tristate driver RXHLOCK on net RXHLOCK has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : coretse_ahb.v(344) | Tristate driver TXHLOCK on net TXHLOCK has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXD_t[0] on net TXD[0] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXD_t[1] on net TXD[1] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXD_t[2] on net TXD[2] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXD_t[3] on net TXD[3] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXD_t[4] on net TXD[4] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXD_t[5] on net TXD[5] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXD_t[6] on net TXD[6] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXD_t[7] on net TXD[7] has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXEN_t on net TXEN has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : | Tristate driver TXER_t on net TXER has its enable tied to GND (module CoreTSE_Webserver_CORETSE_AHB_0_CORETSE_AHB_19s_1s_11s_1s_1s_1s_18s) @W:MO111 : coretse_webserver_osc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module CoreTSE_Webserver_OSC_0_OSC) @W:MO111 : coretse_webserver_osc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module CoreTSE_Webserver_OSC_0_OSC) @W:MO111 : coretse_webserver_osc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module CoreTSE_Webserver_OSC_0_OSC) @W:MO111 : coretse_webserver_osc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module CoreTSE_Webserver_OSC_0_OSC) @W:MO111 : coretse_webserver_osc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module CoreTSE_Webserver_OSC_0_OSC) @W:MO111 : | Tristate driver CORETSE_AHB_0_AHBMTX_HLOCK_t on net CORETSE_AHB_0_AHBMTX_HLOCK has its enable tied to GND (module CoreTSE_Webserver) @W:MO111 : | Tristate driver CORETSE_AHB_0_AHBMRX_HLOCK_t on net CORETSE_AHB_0_AHBMRX_HLOCK has its enable tied to GND (module CoreTSE_Webserver) @W:MO171 : coreresetp.v(769) | Sequential instance CoreResetP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance CoreResetP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance CoreResetP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:MO171 : msgmii_clkrst.v(354) | Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0.CORETSE_AHBOi0.CORETSE_AHBo1i0.CORETSE_AHBoO1 reduced to a combinational gate by constant propagation @W:MO171 : msgmii_clkrst.v(328) | Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0.CORETSE_AHBOi0.CORETSE_AHBo1i0.CORETSE_AHBl010 reduced to a combinational gate by constant propagation @W:MO171 : msgmii_clkrst.v(315) | Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0.CORETSE_AHBOi0.CORETSE_AHBo1i0.CORETSE_AHBI010 reduced to a combinational gate by constant propagation @W:MO171 : pemstat_cntrl.v(406) | Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBlO0i reduced to a combinational gate by constant propagation @W:MO171 : pecar.v(872) | Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBlOIo.CORETSE_AHBO10o reduced to a combinational gate by constant propagation @W:MO171 : pecar.v(886) | Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBlOIo.CORETSE_AHBI10o reduced to a combinational gate by constant propagation @N:BN362 : pecar.v(951) | Removing sequential instance CORETSE_AHBlOIo.CORETSE_AHBi10o of view:PrimLib.sdffr(prim) in hierarchy view:work.pe_mcxmac_0_0s_0s(verilog) because there are no references to its outputs @N:BN362 : pecar.v(907) | Removing sequential instance CORETSE_AHBlOIo.CORETSE_AHBo10o of view:PrimLib.sdffr(prim) in hierarchy view:work.pe_mcxmac_0_0s_0s(verilog) because there are no references to its outputs @N:BN362 : petcr.v(216) | Removing sequential instance CORETSE_AHBi011.CORETSE_AHBliIII of view:PrimLib.sdffr(prim) in hierarchy view:work.msgmii_tbi_0s_1s(verilog) because there are no references to its outputs @N:BN362 : petcr.v(195) | Removing sequential instance CORETSE_AHBi011.CORETSE_AHBOiIII of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_tbi_0s_1s(verilog) because there are no references to its outputs @N:BN362 : petcr.v(181) | Removing sequential instance CORETSE_AHBi011.CORETSE_AHBioIII of view:PrimLib.dff(prim) in hierarchy view:work.msgmii_tbi_0s_1s(verilog) because there are no references to its outputs @W:BN132 : coreresetp.v(963) | Removing sequential instance CoreResetP_0.sdif3_spll_lock_q1, because it is equivalent to instance CoreResetP_0.sdif0_spll_lock_q1 @W:BN132 : coreresetp.v(963) | Removing sequential instance CoreResetP_0.sdif3_spll_lock_q2, because it is equivalent to instance CoreResetP_0.sdif0_spll_lock_q2 Available hyper_sources - for debug and ip models None Found @W:MT462 : coretse_webserver_serdes_if2_0_serdes_if2.v(98) | Net SERDES_IF2_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. @N:FA239 : t8b10b.v(148) | ROM CORETSE_AHBi00oI[5:0] mapped in logic. @N:FA239 : t8b10b.v(148) | ROM CORETSE_AHBI10oI[1:0] mapped in logic. @N:FA239 : t8b10b.v(148) | ROM CORETSE_AHBoOOoI mapped in logic. @N:FA239 : t8b10b.v(148) | ROM CORETSE_AHBO10oI mapped in logic. @N:FA239 : t8b10b.v(148) | ROM CORETSE_AHBi00oI[5:0] mapped in logic. @N:MO106 : t8b10b.v(148) | Found ROM, 'CORETSE_AHBi00oI[5:0]', 32 words by 6 bits @N:FA239 : t8b10b.v(148) | ROM CORETSE_AHBI10oI[1:0] mapped in logic. @N:MO106 : t8b10b.v(148) | Found ROM, 'CORETSE_AHBI10oI[1:0]', 32 words by 2 bits @N:FA239 : t8b10b.v(148) | ROM CORETSE_AHBoOOoI mapped in logic. @N:MO106 : t8b10b.v(148) | Found ROM, 'CORETSE_AHBoOOoI', 32 words by 1 bits @N:FA239 : t8b10b.v(148) | ROM CORETSE_AHBO10oI mapped in logic. @N:MO106 : t8b10b.v(148) | Found ROM, 'CORETSE_AHBO10oI', 32 words by 1 bits @N:FA239 : r10b8b.v(3418) | ROM CORETSE_AHBl1OoI mapped in logic. @N:FA239 : r10b8b.v(3418) | ROM CORETSE_AHBI1OoI mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBiIOoI[2:0] mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBOIOoI[2:0] mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBoIOoI[1:0] mapped in logic. @N:FA239 : r10b8b.v(268) | ROM CORETSE_AHBiOOoI[1:0] mapped in logic. @N:FA239 : r10b8b.v(3418) | ROM CORETSE_AHBl1OoI mapped in logic. @N:MO106 : r10b8b.v(3418) | Found ROM, 'CORETSE_AHBl1OoI', 16 words by 1 bits @N:FA239 : r10b8b.v(3418) | ROM CORETSE_AHBI1OoI mapped in logic. @N:MO106 : r10b8b.v(3418) | Found ROM, 'CORETSE_AHBI1OoI', 16 words by 1 bits @N:FA239 : r10b8b.v(1950) | ROM CORETSE_AHBllOoI[2:0] mapped in logic. @N:MO106 : r10b8b.v(1950) | Found ROM, 'CORETSE_AHBllOoI[2:0]', 12 words by 3 bits @N:FA239 : r10b8b.v(1950) | ROM CORETSE_AHBilOoI mapped in logic. @N:MO106 : r10b8b.v(1950) | Found ROM, 'CORETSE_AHBilOoI', 12 words by 1 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBiIOoI[2:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSE_AHBiIOoI[2:0]', 14 words by 3 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBOIOoI[2:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSE_AHBOIOoI[2:0]', 14 words by 3 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBoIOoI[1:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSE_AHBoIOoI[1:0]', 14 words by 2 bits @N:FA239 : r10b8b.v(268) | ROM CORETSE_AHBiOOoI[1:0] mapped in logic. @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_AHBiOOoI[1:0]', 46 words by 2 bits @N:FA239 : r10b8b.v(3418) | ROM CORETSE_AHBl1OoI mapped in logic. @N:FA239 : r10b8b.v(3418) | ROM CORETSE_AHBI1OoI mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBiIOoI[2:0] mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBOIOoI[2:0] mapped in logic. @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBoIOoI[1:0] mapped in logic. @N:FA239 : r10b8b.v(268) | ROM CORETSE_AHBiOOoI[1:0] mapped in logic. @N:FA239 : r10b8b.v(1950) | ROM CORETSE_AHBllOoI[3:0] mapped in logic. @N:MO106 : r10b8b.v(1950) | Found ROM, 'CORETSE_AHBllOoI[3:0]', 12 words by 4 bits @N:FA239 : r10b8b.v(3418) | ROM CORETSE_AHBl1OoI mapped in logic. @N:MO106 : r10b8b.v(3418) | Found ROM, 'CORETSE_AHBl1OoI', 16 words by 1 bits @N:FA239 : r10b8b.v(3418) | ROM CORETSE_AHBI1OoI mapped in logic. @N:MO106 : r10b8b.v(3418) | Found ROM, 'CORETSE_AHBI1OoI', 16 words by 1 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBiIOoI[2:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSE_AHBiIOoI[2:0]', 14 words by 3 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBOIOoI[2:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSE_AHBOIOoI[2:0]', 14 words by 3 bits @N:FA239 : r10b8b.v(1261) | ROM CORETSE_AHBoIOoI[1:0] mapped in logic. @N:MO106 : r10b8b.v(1261) | Found ROM, 'CORETSE_AHBoIOoI[1:0]', 14 words by 2 bits @N:FA239 : r10b8b.v(268) | ROM CORETSE_AHBiOOoI[1:0] mapped in logic. @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_AHBiOOoI[1:0]', 46 words by 2 bits @N:BN362 : pemgt.v(2142) | Removing sequential instance CORETSE_AHBOiOo[4:0] of view:PrimLib.dffr(prim) in hierarchy view:work.pemgt(verilog) because there are no references to its outputs @N:BN362 : msgmii_cnvtxo.v(414) | Removing sequential instance CORETSE_AHBIl1 of view:PrimLib.dffr(prim) in hierarchy view:work.msgmii_cnvtxo(verilog) because there are no references to its outputs Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 166MB peak: 174MB) @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_2.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[1] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[10] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[11] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[12] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[13] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[14] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[15] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[16] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[25] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[26] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[27] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[1] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_1.SDATASELInt[16] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[1] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_2.SDATASELInt[16] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_2.regHSIZE[0] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_1.regHMASTLOCK is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_2.regHMASTLOCK is always 0, optimizing ... @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_1.regHSIZE[1], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_1.regHTRANS @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_2.regHSIZE[1], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_2.regHTRANS @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[31], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[30] @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[30], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[28] @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[31], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[30] @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[30], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[28] @W:BN132 : coreahblite_masterstage.v(163) | Removing instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29], because it is equivalent to instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[15] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[3] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[0] is always 0, optimizing ... @W:MO197 : coreahblite_slavearbiter.v(449) | FSM register arbRegSMCurrentState[14] removed due to constant propagation @W:MO197 : coreahblite_slavearbiter.v(449) | FSM register arbRegSMCurrentState[2] removed due to constant propagation @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[1] is always 0, optimizing ... Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] is always 0, optimizing ... Encoding state machine state[2:0] (view:work.CoreConfigP_Z6(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z7(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (view:work.CoreResetP_Z7(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled @N: : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z7(verilog) inst count_sdif0[12:0] @N:FX403 : rx4096x36.v(131) | Property "block_ram" or "no_rw_check" found for RAM CORETSE_AHBoo0.CORETSE_AHBooOoI[35:0] with specified coding style. Inferring block RAM. @W:FX107 : rx4096x36.v(131) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : rx4096x36.v(131) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for CORETSE_AHBoo0.CORETSE_AHBooOoI[35:0] (view:work.CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s(verilog)). @N:FX403 : tx2048x40.v(131) | Property "block_ram" or "no_rw_check" found for RAM CORETSE_AHBO10.CORETSE_AHBooOoI[39:0] with specified coding style. Inferring block RAM. @W:FX107 : tx2048x40.v(131) | No read/write conflict check. Possible simulation mismatch! @N:MF707 : tx2048x40.v(131) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for CORETSE_AHBO10.CORETSE_AHBooOoI[39:0] (view:work.CoreTSE_top_19s_1s_11s_12s_1s_1s_1s_18s(verilog)). Encoding state machine CORETSE_AHBOOol[3:0] (view:work.dmatx_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : dmatx.v(566) | No possible illegal states for state machine CORETSE_AHBOOol[3:0],safe FSM implementation is disabled Encoding state machine CORETSE_AHBI0ol[3:0] (view:work.dmatx_0s(verilog)) original code -> new code 000 -> 00 100 -> 01 110 -> 10 111 -> 11 @N:MO225 : dmatx.v(1110) | No possible illegal states for state machine CORETSE_AHBI0ol[3:0],safe FSM implementation is disabled @N:FX404 : dmatx.v(1251) | Found addmux in view:work.dmatx_0s(verilog) inst CORETSE_AHBo1ol[15:0] from un1_CORETSE_AHBl1ol_1[15:0] Encoding state machine CORETSE_AHBI0ol[3:0] (view:work.dmarx_0s(verilog)) original code -> new code 000 -> 00 100 -> 01 110 -> 10 111 -> 11 @N:MO225 : dmarx.v(1039) | No possible illegal states for state machine CORETSE_AHBI0ol[3:0],safe FSM implementation is disabled Encoding state machine CORETSE_AHBOOol[3:0] (view:work.dmarx_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : dmarx.v(501) | No possible illegal states for state machine CORETSE_AHBOOol[3:0],safe FSM implementation is disabled @N:MF179 : amcxtfif_fab.v(762) | Found 11 bit by 11 bit '==' comparator, 'un3_CORETSE_AHBO01I' Encoding state machine CORETSE_AHBOIiI[5:0] (view:work.amcxtfif_sys_11s_32s_2s_0s_0_0_1s(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N:FX404 : amcxtfif_sys.v(1276) | Found addmux in view:work.amcxtfif_sys_11s_32s_2s_0s_0_0_1s(verilog) inst un1_CORETSE_AHBiliI_3_0_m[13:0] from un1_CORETSE_AHBiliI_3_1[13:0] @N:MF179 : amcxtfif_sys.v(2069) | Found 12 bit by 12 bit '==' comparator, 'un1_CORETSE_AHBiliI' Encoding state machine CORETSE_AHBIi0I[4:0] (view:work.amcxrfif_fab_12s_32s_2s_0_1s(verilog)) original code -> new code 0000 -> 00001 1000 -> 00010 1100 -> 00100 1110 -> 01000 1111 -> 10000 @N:MF179 : amcxrfif_fab.v(497) | Found 13 bit by 13 bit '==' comparator, 'un4_CORETSE_AHBil0I' @N: : amcxrfif_sys.v(1963) | Found counter in view:work.amcxrfif_sys_0s_12s_32s_2s_0_0_0_1s(verilog) inst CORETSE_AHBIi1I[13:0] @N:MF179 : amcxrfif_sys.v(1281) | Found 12 bit by 12 bit '==' comparator, 'un3_CORETSE_AHBO01I' Encoding state machine CORETSE_AHBiOOl[5:0] (view:work.amcxtfif_wtm_12s_1s_0_0(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N: : amcxtfif_wtm.v(524) | Found counter in view:work.amcxtfif_wtm_12s_1s_0_0(verilog) inst CORETSE_AHBOIOl[15:0] @N:MF179 : | Found 17 bit by 17 bit '==' comparator, 'un12_CORETSE_AHBO1llI' @N:MF179 : petfn_top.v(9611) | Found 16 bit by 16 bit '==' comparator, 'un18_CORETSE_AHBO1llI' @N:MF179 : petfn_top.v(4272) | Found 16 bit by 16 bit '==' comparator, 'un3_CORETSE_AHBIIOlI' @N:MF179 : petfn_top.v(5110) | Found 10 bit by 10 bit '==' comparator, 'CORETSE_AHBi1OlI' @N: : perfn_top.v(2477) | Found counter in view:work.perfn_top_0s_0_1s(verilog) inst CORETSE_AHBio0OI[14:0] @N:BN362 : perfn_top.v(3664) | Removing sequential instance CORETSE_AHBIIo1[0] of view:PrimLib.dffr(prim) in hierarchy view:work.perfn_top_0s_0_1s(verilog) because there are no references to its outputs @N:BN362 : perfn_top.v(3664) | Removing sequential instance CORETSE_AHBIIo1[1] of view:PrimLib.dffr(prim) in hierarchy view:work.perfn_top_0s_0_1s(verilog) because there are no references to its outputs @N:MF179 : | Found 17 bit by 17 bit '==' comparator, 'un21_CORETSE_AHBoO1OI' @N:MF179 : perfn_top.v(4371) | Found 16 bit by 16 bit '==' comparator, 'un6_CORETSE_AHBOIoOI' Encoding state machine CORETSE_AHBiooo[31:0] (view:work.pemgt(verilog)) original code -> new code 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBiO1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBlI1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBoI1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBiI1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBOl1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBIl1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBll1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBol1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBil1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBO01i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBI01i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBl01i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBo01i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBo11i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBi11i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBOo1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBIo1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBlo1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBoo1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinchd.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBio1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBIi1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sinc.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBli1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBoi1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBii1i.CORETSE_AHBoo0i[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBOOoi.CORETSE_AHBoo0i[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBIOoi.CORETSE_AHBoo0i[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBlOoi.CORETSE_AHBoo0i[11:0] @N: : pemstat_sincnf.v(96) | Found counter in view:work.pemstat(verilog) inst CORETSE_AHBI1li.CORETSE_AHBoOoi.CORETSE_AHBoo0i[11:0] @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[30] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[29] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[28] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[27] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[26] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[25] is always 0, optimizing ... @W:MO160 : pemstat_eim.v(1931) | Register bit CORETSE_AHBo1li.CORETSE_AHBl00i[24] is always 0, optimizing ... @W:MO129 : pemstat_cntrl.v(2167) | Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[36] reduced to a combinational gate by constant propagation @W:MO129 : pemstat_cntrl.v(2167) | Sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[37] reduced to a combinational gate by constant propagation @N: : pemstat_linc.v(96) | Found counter in view:work.pemstat_linc(verilog) inst CORETSE_AHBoo0i[17:0] @N: : mmcxwol.v(964) | Found counter in view:work.mmcxwol(verilog) inst CORETSE_AHBIi00[4:0] @N: : mmcxwol.v(765) | Found counter in view:work.mmcxwol(verilog) inst CORETSE_AHBio00[4:0] @N: : msgmii_cnvtxo.v(267) | Found counter in view:work.msgmii_cnvtxo(verilog) inst CORETSE_AHBii10[6:0] Encoding state machine CORETSE_AHBIii0_1[3:0] (view:work.perex_pcs_0s_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : perex_pcs.v(4633) | No possible illegal states for state machine CORETSE_AHBIii0_1[3:0],safe FSM implementation is disabled @N: : msgmii_peanx_top.v(3370) | Found counter in view:work.msgmii_peanx_top(verilog) inst CORETSE_AHBioI1[20:0] @N:MF179 : msgmii_peanx_top.v(2364) | Found 15 bit by 15 bit '==' comparator, 'un7_CORETSE_AHBo1l1' @N:MF179 : msgmii_peanx_top.v(2656) | Found 16 bit by 16 bit '==' comparator, 'CORETSE_AHBoil1' @N:MF179 : msgmii_peanx_top.v(2980) | Found 15 bit by 15 bit '==' comparator, 'un7_CORETSE_AHBoI01' @N: : msgmii_cnvrxi.v(453) | Found counter in view:work.msgmii_cnvrxi(verilog) inst CORETSE_AHBii10[5:0] @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_2.regHADDR[28] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_2.masterDataInProg[0] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_1.regHADDR[28] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 242MB peak: 253MB) @N:BN362 : petfn_top.v(10292) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[50] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(10292) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[31] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(10292) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[30] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(8708) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBOIllI in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(8613) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBiOllI in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_2.slave_arbiter.arbRegSMCurrentState[10] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_2.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_3.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 230MB peak: 253MB) @N:BN362 : petfn_top.v(9644) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBIIoOI in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(9502) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBi0llI in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(5937) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBI0llI in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(3326) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBllllI in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(10292) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[23] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(10292) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[22] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : petfn_top.v(10292) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[21] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : pemgt.v(547) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBooOo.CORETSE_AHBiooo[31] in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : pemstat_sinc.v(197) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBI1li.CORETSE_AHBli1i.CORETSE_AHBoOIi in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs @N:BN362 : pemstat_sinc.v(197) | Removing sequential instance CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBI1li.CORETSE_AHBIi1i.CORETSE_AHBoOIi in hierarchy view:work.CoreTSE_Webserver(verilog) because there are no references to its outputs Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 223MB peak: 280MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 227MB peak: 280MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:33s; Memory used current: 262MB peak: 280MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:34s; Memory used current: 258MB peak: 280MB) @N:MO106 : r10b8b.v(2472) | Found ROM, 'CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBOoIOI.CORETSE_AHBi0OoI[0:0]', 64 words by 1 bits @N:MO106 : r10b8b.v(2472) | Found ROM, 'CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBloIOI.CORETSE_AHBO1OoI[0:0]', 64 words by 1 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBOoIOI.CORETSE_AHBOOOoI[4:0]', 46 words by 5 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBloIOI.CORETSE_AHBOOOoI[4:0]', 46 words by 5 bits @N:MO106 : r10b8b.v(2472) | Found ROM, 'CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBloIOI.CORETSE_AHBi0OoI', 64 words by 1 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBloIOI.CORETSE_AHBlOOoI[1:0]', 46 words by 2 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBloIOI.CORETSE_AHBoOOoI', 46 words by 1 bits @N:MO106 : r10b8b.v(2472) | Found ROM, 'CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBOoIOI.CORETSE_AHBO1OoI', 64 words by 1 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBOoIOI.CORETSE_AHBlOOoI[1:0]', 46 words by 2 bits @N:MO106 : r10b8b.v(268) | Found ROM, 'CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBOoIOI.CORETSE_AHBoOOoI', 46 words by 1 bits Finished preparing to map (Real Time elapsed 0h:00m:39s; CPU Time elapsed 0h:00m:39s; Memory used current: 261MB peak: 280MB) Finished technology mapping (Real Time elapsed 0h:00m:47s; CPU Time elapsed 0h:00m:46s; Memory used current: 315MB peak: 327MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:47s -3.99ns 9954 / 5143 2 0h:00m:48s -4.03ns 9648 / 5143 3 0h:00m:48s -3.79ns 9650 / 5143 4 0h:00m:48s -3.79ns 9650 / 5143 5 0h:00m:48s -3.79ns 9650 / 5143 @N:FX271 : pehst.v(1713) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1[5]" with 7 loads replicated 1 times to improve timing @N:FX271 : pehst.v(1713) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1[6]" with 6 loads replicated 1 times to improve timing @N:FX271 : pehst.v(1713) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1[2]" with 8 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[10]" with 9 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[9]" with 7 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[15]" with 4 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[14]" with 4 loads replicated 1 times to improve timing @N:FX271 : pehst.v(1609) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBoo01[1]" with 43 loads replicated 3 times to improve timing @N:FX271 : pehst.v(1609) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBoo01[0]" with 34 loads replicated 2 times to improve timing Timing driven replication report Added 12 Registers via timing driven replication Added 0 LUTs via timing driven replication @N:FX271 : petfn_top.v(10292) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[4]" with 6 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[3]" with 11 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[2]" with 10 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[1]" with 9 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[0]" with 9 loads replicated 1 times to improve timing @N:FX271 : petfn_top.v(10292) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[2]" with 9 loads replicated 1 times to improve timing @N:FX271 : petfn_top.v(10292) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[3]" with 9 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[11]" with 9 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[12]" with 5 loads replicated 1 times to improve timing @N:FX271 : petfn_top.v(10292) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[1]" with 7 loads replicated 1 times to improve timing @N:FX271 : petfn_top.v(10292) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[0]" with 7 loads replicated 1 times to improve timing @N:FX271 : petfn_top.v(10292) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[10]" with 6 loads replicated 1 times to improve timing @N:FX271 : petfn_top.v(10292) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[11]" with 6 loads replicated 1 times to improve timing @N:FX271 : permc_top.v(651) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o[13]" with 6 loads replicated 1 times to improve timing @N:FX271 : petfn_top.v(10292) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[13]" with 4 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl1II.N_287_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl1II.N_410_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl1II.N_423_i" with 2 loads replicated 1 times to improve timing @N:FX271 : amcxrfif_sys.v(2080) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl1II.N_415_i" with 2 loads replicated 1 times to improve timing Timing driven replication report Added 15 Registers via timing driven replication Added 12 LUTs via timing driven replication 6 0h:00m:53s -2.79ns 9636 / 5170 7 0h:00m:53s -3.29ns 9639 / 5170 @N:FX271 : pehst.v(1713) | Instance "CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1[3]" with 15 loads replicated 2 times to improve timing Timing driven replication report Added 2 Registers via timing driven replication Added 0 LUTs via timing driven replication 8 0h:00m:54s -2.79ns 9639 / 5172 @N:FP130 : | Promoting Net CoreResetP_0_MSS_HPMS_READY on CLKINT I_2372 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBi010_i on CLKINT I_2373 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBIio1_i on CLKINT I_2374 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI1O1_i on CLKINT I_2375 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBlio1_i on CLKINT I_2376 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBI0II_i on CLKINT I_2377 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBO0II_i on CLKINT I_2378 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBilII_i on CLKINT I_2379 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl0II_i on CLKINT I_2380 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBlOIo.CORETSE_AHBO00o_i on CLKINT I_2381 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBo1i0.un1_CORETSE_AHBOI10_i on CLKINT I_2382 @N:FP130 : | Promoting Net PHY_MDC_c on CLKINT I_2383 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBlOIo.CORETSE_AHBi00o_i on CLKINT I_2384 @N:FP130 : | Promoting Net CoreConfigP_0_APB_S_PRESET_N on CLKINT I_2385 @N:FP130 : | Promoting Net CoreConfigP_0_APB_S_PCLK on CLKINT I_2386 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBo0II_i on CLKINT I_2387 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBlOIo.CORETSE_AHBIl0o_i on CLKINT I_2388 @N:FP130 : | Promoting Net CoreResetP_0.sm0_areset_n_clk_base on CLKINT I_2389 @N:FP130 : | Promoting Net CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBo1i0.un1_CORETSE_AHBoO10_i on CLKINT I_2390 @N:FP130 : | Promoting Net CoreResetP_0.sdif0_areset_n_rcosc on CLKINT I_2391 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:56s; CPU Time elapsed 0h:00m:56s; Memory used current: 273MB peak: 327MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:57s; CPU Time elapsed 0h:00m:57s; Memory used current: 281MB peak: 327MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 8 non-gated/non-generated clock tree(s) driving 5079 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 124 clock pin(s) of sequential element(s) 0 instances converted, 124 sequential instances remain driven by gated/generated clocks ========================================================================================== Non-Gated/Non-Generated Clocks =========================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0002 FCCC_0.GL0_INST CLKINT 2805 CoreTSE_Webserver_MSS_0.MSS_ADLIB_INST ClockId0003 FCCC_3.GL1_INST CLKINT 1397 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBoo0.CORETSE_AHBooOoI_CORETSE_AHBooOoI_0_8 ClockId0004 FCCC_1.GL0_INST CLKINT 408 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0.CORETSE_AHBOi0.CORETSE_AHBlOO1.CORETSE_AHBii10[5] ClockId0005 FCCC_2.GL0_INST CLKINT 333 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBIOI[8] ClockId0006 OSC_0.I_RCOSC_25_50MHZ_FAB_CLKINT CLKINT 30 CoreResetP_0.count_sdif0[12] ClockId0007 FCCC_1.GL1_INST CLKINT 12 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBi011.CORETSE_AHBoiIII ClockId0008 SERDES_IF2_0.refclk1_inbuf_diff INBUF_DIFF 1 SERDES_IF2_0.SERDESIF_INST ClockId0009 CoreTSE_Webserver_MSS_0.MSS_ADLIB_INST clock definition on MSS_075 93 SERDES_IF2_0.SERDESIF_INST ===================================================================================================================================================================================================================== =================================================================================================================================================== Gated/Generated Clocks =================================================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ClockId0001 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBooOo.CORETSE_AHBi01 SLE 124 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOlO1 No gated clock conversion method for cell cell:ACG4.SLE ============================================================================================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:58s; CPU Time elapsed 0h:00m:58s; Memory used current: 197MB peak: 327MB) Writing Analyst data base D:\CASES\coretse\CoreTSE_Webserver\synthesis\synwork\CoreTSE_Webserver_m.srm @W:MT462 : coretse_webserver_serdes_if2_0_serdes_if2.v(98) | Net SERDES_IF2_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. Finished Writing Netlist Databases (Real Time elapsed 0h:01m:00s; CPU Time elapsed 0h:01m:00s; Memory used current: 256MB peak: 327MB) Writing EDIF Netlist and constraint files @W:MT462 : coretse_webserver_serdes_if2_0_serdes_if2.v(98) | Net SERDES_IF2_0.REFCLK1_OUT appears to be an unidentified clock source. Assuming default frequency. @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:01m:03s; CPU Time elapsed 0h:01m:02s; Memory used current: 259MB peak: 327MB) Start final timing analysis (Real Time elapsed 0h:01m:04s; CPU Time elapsed 0h:01m:03s; Memory used current: 247MB peak: 327MB) @W:MT246 : coretse_webserver_fccc_3_fccc.v(37) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) Found clock CLK1_PAD with period 20.00ns Found clock SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] with period 8.00ns Found clock SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] with period 8.00ns Found clock OSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns Found clock FCCC_3/GL0 with period 8.00ns Found clock FCCC_3/GL1 with period 8.00ns Found clock FCCC_2/GL0 with period 8.00ns Found clock FCCC_1/GL0 with period 16.00ns Found clock FCCC_1/GL1 with period 16.00ns Found clock FCCC_0/GL0 with period 20.00ns Found clock CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB with period 80.00ns @W:MT420 : | Found inferred clock pemgt|CORETSE_AHBi01_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBooOo.CORETSE_AHBi01" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Thu Nov 17 15:27:54 2016 # Top view: CoreTSE_Webserver Requested Frequency: 12.5 MHz Wire load mode: top Paths requested: 5 Constraint File(s): D:\CASES\coretse\CoreTSE_Webserver\designer\CoreTSE_Webserver\synthesis.fdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -1.587 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CLK1_PAD 50.0 MHz NA 20.000 NA NA declared default_clkgroup CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB 12.5 MHz 107.9 MHz 80.000 9.270 35.365 declared default_clkgroup FCCC_0/GL0 50.0 MHz 35.8 MHz 20.000 27.933 -1.275 generated (from CLK1_PAD) default_clkgroup FCCC_1/GL0 62.5 MHz 65.8 MHz 16.000 15.192 2.685 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_1/GL1 62.5 MHz 80.2 MHz 16.000 12.466 7.106 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_2/GL0 125.0 MHz 160.4 MHz 8.000 6.233 2.738 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup FCCC_3/GL0 125.0 MHz NA 8.000 NA NA generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup FCCC_3/GL1 125.0 MHz 89.5 MHz 8.000 11.173 -1.587 generated (from SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup OSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 431.2 MHz 20.000 2.319 17.681 declared default_clkgroup SERDES_IF2_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup SERDES_IF2_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup pemgt|CORETSE_AHBi01_inferred_clock 100.0 MHz 152.0 MHz 10.000 6.580 3.420 inferred Inferred_clkgroup_0 System 100.0 MHz 477.6 MHz 10.000 2.094 7.906 system system_clkgroup ================================================================================================================================================================================================= @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 7.906 | No paths - | No paths - | No paths - CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB | 80.000 73.178 | No paths - | 40.000 38.066 | 40.000 35.365 CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB FCCC_0/GL0 | 20.000 False | No paths - | No paths - | No paths - OSC_0/I_RCOSC_25_50MHZ/CLKOUT OSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 17.681 | No paths - | No paths - | No paths - OSC_0/I_RCOSC_25_50MHZ/CLKOUT FCCC_0/GL0 | 20.000 False | No paths - | No paths - | No paths - FCCC_0/GL0 System | 20.000 18.929 | No paths - | No paths - | No paths - FCCC_0/GL0 CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB | 20.000 False | No paths - | No paths - | No paths - FCCC_0/GL0 OSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 False | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_0/GL0 | 20.000 8.504 | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_1/GL0 | 4.000 0.202 | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_1/GL1 | 4.000 0.884 | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_2/GL0 | 4.000 0.884 | No paths - | No paths - | No paths - FCCC_0/GL0 FCCC_3/GL1 | 4.000 -1.275 | No paths - | No paths - | No paths - FCCC_0/GL0 pemgt|CORETSE_AHBi01_inferred_clock | Diff grp - | No paths - | No paths - | No paths - FCCC_1/GL0 FCCC_1/GL0 | 16.000 6.108 | No paths - | No paths - | No paths - FCCC_1/GL0 FCCC_2/GL0 | 8.000 2.685 | No paths - | No paths - | No paths - FCCC_1/GL0 FCCC_3/GL1 | 8.000 3.738 | No paths - | No paths - | No paths - FCCC_1/GL1 FCCC_1/GL0 | 8.000 7.106 | No paths - | No paths - | No paths - FCCC_1/GL1 FCCC_1/GL1 | 16.000 15.106 | No paths - | No paths - | No paths - FCCC_2/GL0 FCCC_1/GL0 | 8.000 5.476 | No paths - | No paths - | No paths - FCCC_2/GL0 FCCC_1/GL1 | 8.000 5.476 | No paths - | No paths - | No paths - FCCC_2/GL0 FCCC_2/GL0 | 8.000 2.738 | No paths - | No paths - | No paths - FCCC_2/GL0 FCCC_3/GL1 | 8.000 6.752 | No paths - | No paths - | No paths - FCCC_2/GL0 pemgt|CORETSE_AHBi01_inferred_clock | Diff grp - | No paths - | No paths - | No paths - FCCC_3/GL1 FCCC_0/GL0 | 4.000 -1.587 | No paths - | No paths - | No paths - FCCC_3/GL1 FCCC_2/GL0 | 8.000 4.650 | No paths - | No paths - | No paths - FCCC_3/GL1 FCCC_3/GL1 | 8.000 0.327 | No paths - | No paths - | No paths - pemgt|CORETSE_AHBi01_inferred_clock FCCC_0/GL0 | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSE_AHBi01_inferred_clock FCCC_1/GL0 | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSE_AHBi01_inferred_clock FCCC_1/GL1 | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSE_AHBi01_inferred_clock FCCC_2/GL0 | Diff grp - | No paths - | No paths - | No paths - pemgt|CORETSE_AHBi01_inferred_clock pemgt|CORETSE_AHBi01_inferred_clock | 10.000 3.420 | No paths - | No paths - | No paths - ========================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CoreConfigP_0.psel CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE Q psel 0.094 35.365 CoreConfigP_0.state[1] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE Q state[1] 0.076 38.066 CoreConfigP_0.SDIF0_PENABLE CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE Q CoreConfigP_0_SDIF0_APBmslave_PENABLE 0.094 38.101 CoreConfigP_0.state[0] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE Q state[0] 0.076 38.745 CoreConfigP_0.paddr[15] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE Q paddr[15] 0.076 38.783 SERDES_IF2_0.SERDESIF_INST CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[25] CoreConfigP_0_SDIF0_APBmslave_PRDATA[25] 5.348 73.178 SERDES_IF2_0.SERDESIF_INST CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[8] CoreConfigP_0_SDIF0_APBmslave_PRDATA[8] 5.255 73.271 SERDES_IF2_0.SERDESIF_INST CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[29] CoreConfigP_0_SDIF0_APBmslave_PRDATA[29] 5.235 73.291 SERDES_IF2_0.SERDESIF_INST CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[24] CoreConfigP_0_SDIF0_APBmslave_PRDATA[24] 5.230 73.296 SERDES_IF2_0.SERDESIF_INST CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PRDATA[28] CoreConfigP_0_SDIF0_APBmslave_PRDATA[28] 5.217 73.309 ============================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF2_0.SERDESIF_INST CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SERDESIF_075 APB_PSEL N_19 37.170 35.365 CoreConfigP_0.FIC_2_APB_M_PRDATA[16] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE D prdata[16] 39.778 36.576 CoreConfigP_0.FIC_2_APB_M_PRDATA[17] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE D prdata[17] 39.778 36.576 CoreConfigP_0.FIC_2_APB_M_PRDATA[18] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE D prdata[18] 39.778 36.576 CoreConfigP_0.FIC_2_APB_M_PRDATA[1] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE D prdata[1] 39.778 37.309 CoreConfigP_0.FIC_2_APB_M_PRDATA[0] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE D prdata[0] 39.778 37.343 CoreConfigP_0.state[1] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE D state_ns[1] 39.778 37.626 CoreConfigP_0.FIC_2_APB_M_PREADY CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE EN N_13_i_0 39.706 37.665 CoreConfigP_0.control_reg_1[0] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE EN control_reg_15 39.706 37.774 CoreConfigP_0.control_reg_1[1] CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB SLE EN control_reg_15 39.706 37.774 ======================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 40.000 - Setup time: 2.830 + Clock delay at ending point: 0.000 (ideal) = Required time: 37.170 - Propagation time: 1.805 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 35.365 Number of logic level(s): 1 Starting point: CoreConfigP_0.psel / Q Ending point: SERDES_IF2_0.SERDESIF_INST / APB_PSEL The start point is clocked by CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB [falling] on pin CLK The end point is clocked by CoreTSE_Webserver_MSS_0/CLK_CONFIG_APB [rising] on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------ CoreConfigP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.637 - 3 CoreConfigP_0.R_SDIF0_PSEL_1_i_o3 CFG2 A In - 0.732 - CoreConfigP_0.R_SDIF0_PSEL_1_i_o3 CFG2 Y Out 0.076 0.807 - N_19 Net - - 0.998 - 36 SERDES_IF2_0.SERDESIF_INST SERDESIF_075 APB_PSEL In - 1.805 - ============================================================================================================ Total path delay (propagation time + setup) of 4.635 is 3.000(64.7%) logic and 1.635(35.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[5] FCCC_0/GL0 SLE Q CORETSE_AHBIii1_fast[5] 0.094 -1.275 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[6] FCCC_0/GL0 SLE Q CORETSE_AHBIii1_fast[6] 0.094 -1.240 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBi1II.CORETSE_AHBIoOI[0] FCCC_0/GL0 SLE Q CORETSE_AHBIoOI[0] 0.094 -1.044 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBi1II.CORETSE_AHBOoOI[1] FCCC_0/GL0 SLE Q CORETSE_AHBOoOI[1] 0.094 -1.032 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBi1II.CORETSE_AHBiIII[13] FCCC_0/GL0 SLE Q CORETSE_AHBiIII[13] 0.076 -1.011 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBi1II.CORETSE_AHBOoOI[0] FCCC_0/GL0 SLE Q CORETSE_AHBOoOI[0] 0.094 -0.990 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[2] FCCC_0/GL0 SLE Q CORETSE_AHBIii1_fast[2] 0.094 -0.951 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1[4] FCCC_0/GL0 SLE Q CORETSE_AHBIii1[4] 0.094 -0.939 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBi1II.CORETSE_AHBOoOI[14] FCCC_0/GL0 SLE Q CORETSE_AHBOoOI[14] 0.094 -0.929 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBi1II.CORETSE_AHBIoOI[1] FCCC_0/GL0 SLE Q CORETSE_AHBIoOI[1] 0.094 -0.922 ========================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o FCCC_0/GL0 SLE D N_593_i_0 3.778 -1.275 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBol1o FCCC_0/GL0 SLE D CORETSE_AHBl11OI 3.778 -1.242 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBiloOI FCCC_0/GL0 SLE D CORETSE_AHBoloOI 3.778 -1.216 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBlilOI FCCC_0/GL0 SLE D N_197_i_0 3.778 -1.081 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl1II.CORETSE_AHBil1I[0] FCCC_0/GL0 SLE EN CORETSE_AHBIOoI 3.707 -1.044 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl1II.CORETSE_AHBil1I[1] FCCC_0/GL0 SLE EN CORETSE_AHBIOoI 3.707 -1.044 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl1II.CORETSE_AHBil1I[2] FCCC_0/GL0 SLE EN CORETSE_AHBIOoI 3.707 -1.044 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl1II.CORETSE_AHBil1I[3] FCCC_0/GL0 SLE EN CORETSE_AHBIOoI 3.707 -1.044 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl1II.CORETSE_AHBil1I[4] FCCC_0/GL0 SLE EN CORETSE_AHBIOoI 3.707 -1.044 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBl1II.CORETSE_AHBil1I[5] FCCC_0/GL0 SLE EN CORETSE_AHBIOoI 3.707 -1.044 ============================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.053 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.275 Number of logic level(s): 8 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[5] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by FCCC_3/GL1 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[5] SLE Q Out 0.094 0.094 - CORETSE_AHBIii1_fast[5] Net - - 0.587 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 CFG2 A In - 0.681 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 CFG2 Y Out 0.087 0.768 - un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 Net - - 0.706 - 8 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0_RNIJIEI CFG4 B In - 1.474 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0_RNIJIEI CFG4 Y Out 0.143 1.617 - un22_CORETSE_AHBoI0OI_5 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_axb_5_i CFG2 A In - 2.207 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_axb_5_i CFG2 Y Out 0.087 2.294 - un22_CORETSE_AHBoI0OI_axb_5_i_0 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_5 ARI1 C In - 2.777 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_5 ARI1 FCO Out 0.228 3.005 - un22_CORETSE_AHBoI0OI_cry_5 Net - - 0.000 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_6 ARI1 FCI In - 3.005 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_6 ARI1 FCO Out 0.013 3.018 - un22_CORETSE_AHBoI0OI_cry_6 Net - - 0.000 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_7 ARI1 FCI In - 3.018 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_7 ARI1 FCO Out 0.013 3.031 - un22_CORETSE_AHBoI0OI_cry_7 Net - - 0.882 - 4 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un1_CORETSE_AHBoI0OI_i_m2[0] CFG3 C In - 3.913 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un1_CORETSE_AHBoI0OI_i_m2[0] CFG3 Y Out 0.177 4.090 - N_300 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o_RNO CFG4 D In - 4.680 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o_RNO CFG4 Y Out 0.236 4.915 - N_593_i_0 Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o SLE D In - 5.053 - ========================================================================================================================================================================================================= Total path delay (propagation time + setup) of 5.275 is 1.299(24.6%) logic and 3.976(75.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.041 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.263 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[5] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by FCCC_3/GL1 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[5] SLE Q Out 0.094 0.094 - CORETSE_AHBIii1_fast[5] Net - - 0.587 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 CFG2 A In - 0.681 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 CFG2 Y Out 0.087 0.768 - un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 Net - - 0.706 - 8 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0_RNIJIEI CFG4 B In - 1.474 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0_RNIJIEI CFG4 Y Out 0.143 1.617 - un22_CORETSE_AHBoI0OI_5 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_axb_6_i CFG2 A In - 2.207 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_axb_6_i CFG2 Y Out 0.087 2.294 - un22_CORETSE_AHBoI0OI_axb_6_i_0 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_6 ARI1 C In - 2.777 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_6 ARI1 FCO Out 0.228 3.005 - un22_CORETSE_AHBoI0OI_cry_6 Net - - 0.000 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_7 ARI1 FCI In - 3.005 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_7 ARI1 FCO Out 0.013 3.018 - un22_CORETSE_AHBoI0OI_cry_7 Net - - 0.882 - 4 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un1_CORETSE_AHBoI0OI_i_m2[0] CFG3 C In - 3.900 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un1_CORETSE_AHBoI0OI_i_m2[0] CFG3 Y Out 0.177 4.077 - N_300 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o_RNO CFG4 D In - 4.667 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o_RNO CFG4 Y Out 0.236 4.903 - N_593_i_0 Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o SLE D In - 5.041 - ========================================================================================================================================================================================================= Total path delay (propagation time + setup) of 5.263 is 1.287(24.4%) logic and 3.976(75.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.028 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.250 Number of logic level(s): 6 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[5] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by FCCC_3/GL1 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[5] SLE Q Out 0.094 0.094 - CORETSE_AHBIii1_fast[5] Net - - 0.587 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 CFG2 A In - 0.681 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 CFG2 Y Out 0.087 0.768 - un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 Net - - 0.706 - 8 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0_RNIJIEI CFG4 B In - 1.474 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0_RNIJIEI CFG4 Y Out 0.143 1.617 - un22_CORETSE_AHBoI0OI_5 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_axb_7_i CFG2 A In - 2.207 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_axb_7_i CFG2 Y Out 0.087 2.294 - un22_CORETSE_AHBoI0OI_axb_7_i_0 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_7 ARI1 C In - 2.777 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_7 ARI1 FCO Out 0.228 3.005 - un22_CORETSE_AHBoI0OI_cry_7 Net - - 0.882 - 4 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un1_CORETSE_AHBoI0OI_i_m2[0] CFG3 C In - 3.888 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un1_CORETSE_AHBoI0OI_i_m2[0] CFG3 Y Out 0.177 4.064 - N_300 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o_RNO CFG4 D In - 4.654 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o_RNO CFG4 Y Out 0.236 4.890 - N_593_i_0 Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o SLE D In - 5.028 - ========================================================================================================================================================================================================= Total path delay (propagation time + setup) of 5.250 is 1.274(24.3%) logic and 3.976(75.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.018 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.240 Number of logic level(s): 8 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[6] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by FCCC_3/GL1 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[6] SLE Q Out 0.094 0.094 - CORETSE_AHBIii1_fast[6] Net - - 0.509 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 CFG2 B In - 0.603 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 CFG2 Y Out 0.129 0.732 - un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 Net - - 0.706 - 8 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0_RNIJIEI CFG4 B In - 1.438 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0_RNIJIEI CFG4 Y Out 0.143 1.581 - un22_CORETSE_AHBoI0OI_5 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_axb_5_i CFG2 A In - 2.171 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_axb_5_i CFG2 Y Out 0.087 2.258 - un22_CORETSE_AHBoI0OI_axb_5_i_0 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_5 ARI1 C In - 2.742 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_5 ARI1 FCO Out 0.228 2.970 - un22_CORETSE_AHBoI0OI_cry_5 Net - - 0.000 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_6 ARI1 FCI In - 2.970 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_6 ARI1 FCO Out 0.013 2.982 - un22_CORETSE_AHBoI0OI_cry_6 Net - - 0.000 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_7 ARI1 FCI In - 2.982 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_7 ARI1 FCO Out 0.013 2.995 - un22_CORETSE_AHBoI0OI_cry_7 Net - - 0.882 - 4 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un1_CORETSE_AHBoI0OI_i_m2[0] CFG3 C In - 3.877 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un1_CORETSE_AHBoI0OI_i_m2[0] CFG3 Y Out 0.177 4.054 - N_300 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o_RNO CFG4 D In - 4.644 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o_RNO CFG4 Y Out 0.236 4.880 - N_593_i_0 Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o SLE D In - 5.018 - ========================================================================================================================================================================================================= Total path delay (propagation time + setup) of 5.240 is 1.342(25.6%) logic and 3.898(74.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.005 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.227 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[6] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o / D The start point is clocked by FCCC_0/GL0 [rising] on pin CLK The end point is clocked by FCCC_3/GL1 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBliOo.CORETSE_AHBIii1_fast[6] SLE Q Out 0.094 0.094 - CORETSE_AHBIii1_fast[6] Net - - 0.509 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 CFG2 B In - 0.603 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 CFG2 Y Out 0.129 0.732 - un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0 Net - - 0.706 - 8 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0_RNIJIEI CFG4 B In - 1.438 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un6_CORETSE_AHBoI0OI_0_ac0_7_0_a0_0_RNIJIEI CFG4 Y Out 0.143 1.581 - un22_CORETSE_AHBoI0OI_5 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_axb_6_i CFG2 A In - 2.171 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_axb_6_i CFG2 Y Out 0.087 2.258 - un22_CORETSE_AHBoI0OI_axb_6_i_0 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_6 ARI1 C In - 2.742 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_6 ARI1 FCO Out 0.228 2.970 - un22_CORETSE_AHBoI0OI_cry_6 Net - - 0.000 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_7 ARI1 FCI In - 2.970 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un22_CORETSE_AHBoI0OI_cry_7 ARI1 FCO Out 0.013 2.982 - un22_CORETSE_AHBoI0OI_cry_7 Net - - 0.882 - 4 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un1_CORETSE_AHBoI0OI_i_m2[0] CFG3 C In - 3.865 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.un1_CORETSE_AHBoI0OI_i_m2[0] CFG3 Y Out 0.177 4.041 - N_300 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o_RNO CFG4 D In - 4.631 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o_RNO CFG4 Y Out 0.236 4.867 - N_593_i_0 Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBoOlo.CORETSE_AHBil1o SLE D In - 5.005 - ========================================================================================================================================================================================================= Total path delay (propagation time + setup) of 5.227 is 1.329(25.4%) logic and 3.898(74.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_1/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[5] FCCC_1/GL0 SLE Q CORETSE_AHBoIO1[5] 0.094 2.685 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[2] FCCC_1/GL0 SLE Q CORETSE_AHBoIO1[2] 0.094 2.767 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[13] FCCC_1/GL0 SLE Q CORETSE_AHBoIO1[13] 0.094 2.834 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[3] FCCC_1/GL0 SLE Q CORETSE_AHBoIO1[3] 0.094 2.857 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[9] FCCC_1/GL0 SLE Q CORETSE_AHBoIO1[9] 0.094 2.874 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[12] FCCC_1/GL0 SLE Q CORETSE_AHBoIO1[12] 0.094 2.902 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[11] FCCC_1/GL0 SLE Q CORETSE_AHBoIO1[11] 0.094 3.269 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[15] FCCC_1/GL0 SLE Q CORETSE_AHBoIO1[15] 0.094 3.394 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[1] FCCC_1/GL0 SLE Q CORETSE_AHBoIO1[1] 0.094 3.396 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[6] FCCC_1/GL0 SLE Q CORETSE_AHBoIO1[6] 0.094 3.429 =============================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBOlI1 FCCC_1/GL0 SLE D CORETSE_AHBIOI1 7.778 2.685 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBl001 FCCC_1/GL0 SLE D CORETSE_AHBO001 7.778 3.215 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBool1[0] FCCC_1/GL0 SLE D CORETSE_AHBlol1[0] 7.778 3.283 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBO101 FCCC_1/GL0 SLE D CORETSE_AHBi001 7.778 3.302 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBool1[1] FCCC_1/GL0 SLE D CORETSE_AHBlol1[1] 7.778 3.342 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBiII1 FCCC_1/GL0 SLE D N_1069_i_1 7.778 3.415 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBo001 FCCC_1/GL0 SLE D CORETSE_N_11_mux 7.778 3.436 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBIlI1 FCCC_1/GL0 SLE D CORETSE_AHBlOI1 7.778 3.507 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBoII1 FCCC_1/GL0 SLE D N_1071_i_1 7.778 3.565 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBllI1 FCCC_1/GL0 SLE D CORETSE_AHBoOI1 7.778 3.589 ============================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 5.093 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.685 Number of logic level(s): 6 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[5] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBOlI1 / D The start point is clocked by FCCC_1/GL0 [rising] on pin CLK The end point is clocked by FCCC_2/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBil11.CORETSE_AHBoIO1[5] SLE Q Out 0.094 0.094 - CORETSE_AHBoIO1[5] Net - - 0.909 - 8 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.un2_CORETSE_AHBOOI1_i_0_a2_12_3 CFG4 D In - 1.004 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.un2_CORETSE_AHBOOI1_i_0_a2_12_3 CFG4 Y Out 0.276 1.280 - un2_CORETSE_AHBOOI1_i_0_a2_12_3 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.un2_CORETSE_AHBOOI1_i_0_a2_12 CFG4 B In - 1.763 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.un2_CORETSE_AHBOOI1_i_0_a2_12 CFG4 Y Out 0.143 1.906 - un2_CORETSE_AHBOOI1_i_0_a2_12 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.un2_CORETSE_AHBOOI1_i_0_a2_12_RNIBCQT CFG4 D In - 2.496 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.un2_CORETSE_AHBOOI1_i_0_a2_12_RNIBCQT CFG4 Y Out 0.236 2.732 - N_2009 Net - - 0.670 - 6 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBlOI1_0 CFG4 D In - 3.402 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBlOI1_0 CFG4 Y Out 0.284 3.685 - CORETSE_AHBlOI1 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBIOI1_0_a2 CFG4 B In - 4.275 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBIOI1_0_a2 CFG4 Y Out 0.129 4.404 - N_1632 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBIOI1_0 CFG3 A In - 4.888 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBIOI1_0 CFG3 Y Out 0.067 4.955 - CORETSE_AHBIOI1 Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBOlI1 SLE D In - 5.093 - ================================================================================================================================================================================================== Total path delay (propagation time + setup) of 5.315 is 1.451(27.3%) logic and 3.863(72.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_1/GL1 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[0] FCCC_1/GL1 SLE Q CORETSE_AHBooIOI[0] 0.076 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[1] FCCC_1/GL1 SLE Q CORETSE_AHBooIOI[1] 0.076 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[2] FCCC_1/GL1 SLE Q CORETSE_AHBooIOI[2] 0.076 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[3] FCCC_1/GL1 SLE Q CORETSE_AHBooIOI[3] 0.076 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[4] FCCC_1/GL1 SLE Q CORETSE_AHBooIOI[4] 0.076 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[5] FCCC_1/GL1 SLE Q CORETSE_AHBooIOI[5] 0.076 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[6] FCCC_1/GL1 SLE Q CORETSE_AHBooIOI[6] 0.076 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[7] FCCC_1/GL1 SLE Q CORETSE_AHBooIOI[7] 0.076 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[8] FCCC_1/GL1 SLE Q CORETSE_AHBooIOI[8] 0.076 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[9] FCCC_1/GL1 SLE Q CORETSE_AHBooIOI[9] 0.076 7.106 =============================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[0] FCCC_1/GL1 SLE D CORETSE_AHBooIOI[0] 7.778 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[1] FCCC_1/GL1 SLE D CORETSE_AHBooIOI[1] 7.778 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[2] FCCC_1/GL1 SLE D CORETSE_AHBooIOI[2] 7.778 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[3] FCCC_1/GL1 SLE D CORETSE_AHBooIOI[3] 7.778 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[4] FCCC_1/GL1 SLE D CORETSE_AHBooIOI[4] 7.778 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[5] FCCC_1/GL1 SLE D CORETSE_AHBooIOI[5] 7.778 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[6] FCCC_1/GL1 SLE D CORETSE_AHBooIOI[6] 7.778 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[7] FCCC_1/GL1 SLE D CORETSE_AHBooIOI[7] 7.778 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[8] FCCC_1/GL1 SLE D CORETSE_AHBooIOI[8] 7.778 7.106 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[9] FCCC_1/GL1 SLE D CORETSE_AHBooIOI[9] 7.778 7.106 ================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 0.672 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.106 Number of logic level(s): 0 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[0] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[0] / D The start point is clocked by FCCC_1/GL1 [rising] on pin CLK The end point is clocked by FCCC_1/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBooIOI[0] SLE Q Out 0.076 0.076 - CORETSE_AHBooIOI[0] Net - - 0.596 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBol11.CORETSE_AHBioIOI[0] SLE D In - 0.672 - ================================================================================================================================================================================ Total path delay (propagation time + setup) of 0.894 is 0.298(33.3%) logic and 0.596(66.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_2/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBiio[0] FCCC_2/GL0 SLE Q CORETSE_AHBiio[0] 0.094 2.738 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBio0II FCCC_2/GL0 SLE Q CORETSE_AHBio0II 0.094 2.752 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBIi0II[1] FCCC_2/GL0 SLE Q CORETSE_AHBIi0II[1] 0.094 2.768 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBIi0II[2] FCCC_2/GL0 SLE Q CORETSE_AHBIi0II[2] 0.076 2.800 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBiio[1] FCCC_2/GL0 SLE Q CORETSE_AHBiio[1] 0.094 2.814 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBIi0II[0] FCCC_2/GL0 SLE Q CORETSE_AHBIi0II[0] 0.076 2.816 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBiio[2] FCCC_2/GL0 SLE Q CORETSE_AHBiio[2] 0.094 2.881 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBOo0II FCCC_2/GL0 SLE Q CORETSE_AHBOo0II 0.094 2.890 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBlo0II FCCC_2/GL0 SLE Q CORETSE_AHBlo0II 0.094 2.930 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBOO1II FCCC_2/GL0 SLE Q CORETSE_AHBOO1II 0.094 2.987 =============================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBlO1II[7] FCCC_2/GL0 SLE D CORETSE_AHBIO1II[7] 7.778 2.738 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBlO1II[9] FCCC_2/GL0 SLE D CORETSE_AHBIO1II[9] 7.778 2.738 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBlO1II[6] FCCC_2/GL0 SLE D CORETSE_AHBIO1II[6] 7.778 2.749 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBiolII FCCC_2/GL0 SLE D N_1091_i_0 7.778 2.752 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBlO1II[8] FCCC_2/GL0 SLE D CORETSE_AHBIO1II[8] 7.778 2.831 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBlolII FCCC_2/GL0 SLE D CORETSE_AHBi1lII 7.778 3.301 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBl1lII FCCC_2/GL0 SLE D un1_CORETSE_AHBI1lII_0_0[0] 7.778 3.378 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBoolII FCCC_2/GL0 SLE D CORETSE_AHBOolII 7.778 3.394 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBO011.CORETSE_AHBOlI1 FCCC_2/GL0 SLE D CORETSE_AHBIOI1 7.778 3.436 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBiI1II FCCC_2/GL0 SLE D CORETSE_AHBoI1II 7.778 3.481 ======================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.778 - Propagation time: 5.040 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.738 Number of logic level(s): 6 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBiio[0] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBlO1II[9] / D The start point is clocked by FCCC_2/GL0 [rising] on pin CLK The end point is clocked by FCCC_2/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBiio[0] SLE Q Out 0.094 0.094 - CORETSE_AHBiio[0] Net - - 0.923 - 18 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.CORETSE_AHBi00oI_5_0_.m4 CFG3 C In - 1.017 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.CORETSE_AHBi00oI_5_0_.m4 CFG3 Y Out 0.196 1.213 - N_5 Net - - 0.548 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.CORETSE_AHBI10oI_1_0_.m5 CFG3 B In - 1.761 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.CORETSE_AHBI10oI_1_0_.m5 CFG3 Y Out 0.143 1.904 - CORETSE_AHBI10oI[0] Net - - 0.622 - 4 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.CORETSE_AHBlo0oI234_3_RNISR592[0] CFG4 B In - 2.526 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.CORETSE_AHBlo0oI234_3_RNISR592[0] CFG4 Y Out 0.129 2.655 - r_m3_ns_1 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.CORETSE_AHBlo0oI226_1_0_RNI61KT4[0] CFG4 C In - 3.138 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.CORETSE_AHBlo0oI226_1_0_RNI61KT4[0] CFG4 Y Out 0.196 3.334 - CORETSE_AHBlo0oI226_1_0_RNI61KT4[0] Net - - 0.548 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.un1_CORETSE_AHBlo0oI234_2 CFG4 C In - 3.882 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.un1_CORETSE_AHBlo0oI234_2 CFG4 Y Out 0.194 4.076 - un1_CORETSE_AHBlo0oI234_1 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.CORETSE_AHBlo0oI_iv[6] CFG4 D In - 4.666 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBo01II.CORETSE_AHBlo0oI_iv[6] CFG4 Y Out 0.236 4.902 - CORETSE_AHBIO1II[9] Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBiI11.CORETSE_AHBlO1II[9] SLE D In - 5.040 - ================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 5.262 is 1.411(26.8%) logic and 3.851(73.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FCCC_3/GL1 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o_fast[10] FCCC_3/GL1 SLE Q CORETSE_AHBl1o_fast[10] 0.094 -1.587 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[5] FCCC_3/GL1 SLE Q CORETSE_AHBlOo1[5] 0.094 -1.494 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[7] FCCC_3/GL1 SLE Q CORETSE_AHBlOo1[7] 0.094 -1.476 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBO1II.CORETSE_AHBllOI[12] FCCC_3/GL1 SLE Q CORETSE_AHBllOI[12] 0.094 -1.463 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1_fast[3] FCCC_3/GL1 SLE Q CORETSE_AHBlOo1_fast[3] 0.094 -1.456 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1_fast[10] FCCC_3/GL1 SLE Q CORETSE_AHBlOo1_fast[10] 0.094 -1.434 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBoOooI.CORETSE_AHBO1II.CORETSE_AHBllOI[4] FCCC_3/GL1 SLE Q CORETSE_AHBllOI[4] 0.094 -1.407 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1_fast[2] FCCC_3/GL1 SLE Q CORETSE_AHBlOo1_fast[2] 0.094 -1.397 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[8] FCCC_3/GL1 SLE Q CORETSE_AHBlOo1[8] 0.094 -1.374 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o_fast[9] FCCC_3/GL1 SLE Q CORETSE_AHBl1o_fast[9] 0.094 -1.366 =========================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[10] FCCC_3/GL1 SLE D CORETSE_AHBiO0i[10] 3.778 -1.587 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[11] FCCC_3/GL1 SLE D CORETSE_AHBiO0i[11] 3.778 -1.587 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[12] FCCC_3/GL1 SLE D CORETSE_AHBiO0i[12] 3.778 -1.587 CoreTSE_Webserver_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[12] CoreAHBLite_0_AHBmslave3_HRDATA_m[12] 3.009 -1.463 CoreTSE_Webserver_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[4] CoreAHBLite_0_AHBmslave3_HRDATA_m[4] 3.010 -1.407 CoreTSE_Webserver_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[5] CoreAHBLite_0_AHBmslave3_HRDATA_m[5] 3.024 -1.301 CoreTSE_Webserver_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[8] CoreAHBLite_0_AHBmslave3_HRDATA_m[8] 3.005 -1.281 CoreTSE_Webserver_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[6] CoreAHBLite_0_AHBmslave3_HRDATA_m[6] 3.053 -1.272 CoreTSE_Webserver_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[22] CoreAHBLite_0_AHBmslave3_HRDATA_m[22] 2.645 -1.269 CoreTSE_Webserver_MSS_0.MSS_ADLIB_INST FCCC_3/GL1 MSS_075 F_HM0_RDATA[9] CoreAHBLite_0_AHBmslave3_HRDATA_m[9] 2.966 -1.198 ===================================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.365 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.587 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o_fast[10] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[10] / D The start point is clocked by FCCC_3/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o_fast[10] SLE Q Out 0.094 0.094 - CORETSE_AHBl1o_fast[10] Net - - 0.708 - 5 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0_sx CFG4 D In - 0.802 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0_sx CFG4 Y Out 0.276 1.078 - un91_CORETSE_AHBiO0ilto10_d_0_sx Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0 CFG4 D In - 1.561 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0 CFG4 Y Out 0.236 1.797 - un91_CORETSE_AHBiO0ilto10_d_0 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3 CFG4 B In - 2.281 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3 CFG4 Y Out 0.143 2.424 - un91_CORETSE_AHBiO0ilto10_d_3 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3_RNIOAK48 CFG4 D In - 2.907 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3_RNIOAK48 CFG4 Y Out 0.236 3.143 - CORETSE_AHBiO0i[5] Net - - 0.548 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] CFG4 C In - 3.691 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] CFG4 Y Out 0.177 3.867 - CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x[10] CFG4 B In - 4.351 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x[10] CFG4 Y Out 0.143 4.494 - CORETSE_AHBiO0i_0_0_a2_2_1_x[10] Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2[10] CFG4 B In - 5.084 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2[10] CFG4 Y Out 0.143 5.227 - CORETSE_AHBiO0i[10] Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[10] SLE D In - 5.365 - ====================================================================================================================================================================================================== Total path delay (propagation time + setup) of 5.587 is 1.670(29.9%) logic and 3.917(70.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.365 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.587 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o_fast[10] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[12] / D The start point is clocked by FCCC_3/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o_fast[10] SLE Q Out 0.094 0.094 - CORETSE_AHBl1o_fast[10] Net - - 0.708 - 5 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0_sx CFG4 D In - 0.802 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0_sx CFG4 Y Out 0.276 1.078 - un91_CORETSE_AHBiO0ilto10_d_0_sx Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0 CFG4 D In - 1.561 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0 CFG4 Y Out 0.236 1.797 - un91_CORETSE_AHBiO0ilto10_d_0 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3 CFG4 B In - 2.281 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3 CFG4 Y Out 0.143 2.424 - un91_CORETSE_AHBiO0ilto10_d_3 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3_RNIOAK48 CFG4 D In - 2.907 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3_RNIOAK48 CFG4 Y Out 0.236 3.143 - CORETSE_AHBiO0i[5] Net - - 0.548 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] CFG4 C In - 3.691 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] CFG4 Y Out 0.177 3.867 - CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x[10] CFG4 B In - 4.351 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x[10] CFG4 Y Out 0.143 4.494 - CORETSE_AHBiO0i_0_0_a2_2_1_x[10] Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2[12] CFG4 B In - 5.084 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2[12] CFG4 Y Out 0.143 5.227 - CORETSE_AHBiO0i[12] Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[12] SLE D In - 5.365 - ====================================================================================================================================================================================================== Total path delay (propagation time + setup) of 5.587 is 1.670(29.9%) logic and 3.917(70.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.365 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.587 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o_fast[10] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[11] / D The start point is clocked by FCCC_3/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBiOlo.CORETSE_AHBl1o_fast[10] SLE Q Out 0.094 0.094 - CORETSE_AHBl1o_fast[10] Net - - 0.708 - 5 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0_sx CFG4 D In - 0.802 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0_sx CFG4 Y Out 0.276 1.078 - un91_CORETSE_AHBiO0ilto10_d_0_sx Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0 CFG4 D In - 1.561 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0 CFG4 Y Out 0.236 1.797 - un91_CORETSE_AHBiO0ilto10_d_0 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3 CFG4 B In - 2.281 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3 CFG4 Y Out 0.143 2.424 - un91_CORETSE_AHBiO0ilto10_d_3 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3_RNIOAK48 CFG4 D In - 2.907 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3_RNIOAK48 CFG4 Y Out 0.236 3.143 - CORETSE_AHBiO0i[5] Net - - 0.548 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] CFG4 C In - 3.691 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] CFG4 Y Out 0.177 3.867 - CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x[10] CFG4 B In - 4.351 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x[10] CFG4 Y Out 0.143 4.494 - CORETSE_AHBiO0i_0_0_a2_2_1_x[10] Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2[11] CFG4 B In - 5.084 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2[11] CFG4 Y Out 0.143 5.227 - CORETSE_AHBiO0i[11] Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[11] SLE D In - 5.365 - ====================================================================================================================================================================================================== Total path delay (propagation time + setup) of 5.587 is 1.670(29.9%) logic and 3.917(70.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.272 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.494 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[5] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[10] / D The start point is clocked by FCCC_3/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[5] SLE Q Out 0.094 0.094 - CORETSE_AHBlOo1[5] Net - - 0.587 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un1_CORETSE_AHBOI0i[5] CFG4 C In - 0.681 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un1_CORETSE_AHBOI0i[5] CFG4 Y Out 0.182 0.863 - un1_CORETSE_AHBOI0i[5] Net - - 0.648 - 5 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0 CFG4 C In - 1.511 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0 CFG4 Y Out 0.194 1.704 - un91_CORETSE_AHBiO0ilto10_d_0 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3 CFG4 B In - 2.188 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3 CFG4 Y Out 0.143 2.331 - un91_CORETSE_AHBiO0ilto10_d_3 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3_RNIOAK48 CFG4 D In - 2.814 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3_RNIOAK48 CFG4 Y Out 0.236 3.050 - CORETSE_AHBiO0i[5] Net - - 0.548 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] CFG4 C In - 3.598 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] CFG4 Y Out 0.177 3.775 - CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x[10] CFG4 B In - 4.258 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x[10] CFG4 Y Out 0.143 4.401 - CORETSE_AHBiO0i_0_0_a2_2_1_x[10] Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2[10] CFG4 B In - 4.991 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2[10] CFG4 Y Out 0.143 5.134 - CORETSE_AHBiO0i[10] Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[10] SLE D In - 5.272 - ====================================================================================================================================================================================================== Total path delay (propagation time + setup) of 5.494 is 1.534(27.9%) logic and 3.960(72.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.778 - Propagation time: 5.272 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.494 Number of logic level(s): 7 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[5] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[12] / D The start point is clocked by FCCC_3/GL1 [rising] on pin CLK The end point is clocked by FCCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBiOooI.CORETSE_AHBl1Oo.CORETSE_AHBIOlo.CORETSE_AHBlOo1[5] SLE Q Out 0.094 0.094 - CORETSE_AHBlOo1[5] Net - - 0.587 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un1_CORETSE_AHBOI0i[5] CFG4 C In - 0.681 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un1_CORETSE_AHBOI0i[5] CFG4 Y Out 0.182 0.863 - un1_CORETSE_AHBOI0i[5] Net - - 0.648 - 5 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0 CFG4 C In - 1.511 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_0 CFG4 Y Out 0.194 1.704 - un91_CORETSE_AHBiO0ilto10_d_0 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3 CFG4 B In - 2.188 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3 CFG4 Y Out 0.143 2.331 - un91_CORETSE_AHBiO0ilto10_d_3 Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3_RNIOAK48 CFG4 D In - 2.814 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.un91_CORETSE_AHBiO0ilto10_d_3_RNIOAK48 CFG4 Y Out 0.236 3.050 - CORETSE_AHBiO0i[5] Net - - 0.548 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] CFG4 C In - 3.598 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] CFG4 Y Out 0.177 3.775 - CORETSE_AHBiO0i_0_0_a2_2_1_x_sx[10] Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x[10] CFG4 B In - 4.258 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2_2_1_x[10] CFG4 Y Out 0.143 4.401 - CORETSE_AHBiO0i_0_0_a2_2_1_x[10] Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2[12] CFG4 B In - 4.991 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBiO0i_0_0_a2[12] CFG4 Y Out 0.143 5.134 - CORETSE_AHBiO0i[12] Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBilI.CORETSE_AHBOlooI\.CORETSE_AHBO0ooI.CORETSE_AHBO1li.CORETSE_AHBIIIi[12] SLE D In - 5.272 - ====================================================================================================================================================================================================== Total path delay (propagation time + setup) of 5.494 is 1.534(27.9%) logic and 3.960(72.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: OSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------ CoreResetP_0.count_sdif0[0] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[0] 0.094 17.681 CoreResetP_0.count_sdif0[1] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[1] 0.094 17.746 CoreResetP_0.count_sdif0[2] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[2] 0.094 17.760 CoreResetP_0.count_sdif0[3] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[3] 0.094 17.774 CoreResetP_0.count_sdif0[4] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[4] 0.094 17.789 CoreResetP_0.count_sdif0[5] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[5] 0.094 17.803 CoreResetP_0.count_sdif0[6] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[6] 0.094 17.817 CoreResetP_0.count_sdif0[7] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[7] 0.094 17.831 CoreResetP_0.count_sdif0[8] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[8] 0.094 17.845 CoreResetP_0.count_sdif0[9] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif0[9] 0.094 17.858 ======================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------- CoreResetP_0.count_sdif0[12] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[12] 19.778 17.681 CoreResetP_0.count_sdif0[11] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[11] 19.778 17.695 CoreResetP_0.count_sdif0[10] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[10] 19.778 17.709 CoreResetP_0.count_sdif0[9] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[9] 19.778 17.724 CoreResetP_0.count_sdif0[8] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[8] 19.778 17.738 CoreResetP_0.count_sdif0[7] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[7] 19.778 17.752 CoreResetP_0.count_sdif0[6] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[6] 19.778 17.766 CoreResetP_0.count_sdif0[5] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[5] 19.778 17.780 CoreResetP_0.count_sdif0[4] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[4] 19.778 17.794 CoreResetP_0.count_sdif0[3] OSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif0_s[3] 19.778 17.809 ============================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.778 - Propagation time: 2.097 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 17.681 Number of logic level(s): 13 Starting point: CoreResetP_0.count_sdif0[0] / Q Ending point: CoreResetP_0.count_sdif0[12] / D The start point is clocked by OSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK The end point is clocked by OSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- CoreResetP_0.count_sdif0[0] SLE Q Out 0.094 0.094 - count_sdif0[0] Net - - 0.637 - 3 CoreResetP_0.count_sdif0_s_2276 ARI1 B In - 0.732 - CoreResetP_0.count_sdif0_s_2276 ARI1 FCO Out 0.174 0.906 - count_sdif0_s_2276_FCO Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[1] ARI1 FCI In - 0.906 - CoreResetP_0.count_sdif0_cry[1] ARI1 FCO Out 0.014 0.920 - count_sdif0_cry[1] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[2] ARI1 FCI In - 0.920 - CoreResetP_0.count_sdif0_cry[2] ARI1 FCO Out 0.014 0.935 - count_sdif0_cry[2] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[3] ARI1 FCI In - 0.935 - CoreResetP_0.count_sdif0_cry[3] ARI1 FCO Out 0.014 0.949 - count_sdif0_cry[3] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[4] ARI1 FCI In - 0.949 - CoreResetP_0.count_sdif0_cry[4] ARI1 FCO Out 0.014 0.963 - count_sdif0_cry[4] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[5] ARI1 FCI In - 0.963 - CoreResetP_0.count_sdif0_cry[5] ARI1 FCO Out 0.014 0.977 - count_sdif0_cry[5] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[6] ARI1 FCI In - 0.977 - CoreResetP_0.count_sdif0_cry[6] ARI1 FCO Out 0.014 0.991 - count_sdif0_cry[6] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[7] ARI1 FCI In - 0.991 - CoreResetP_0.count_sdif0_cry[7] ARI1 FCO Out 0.014 1.006 - count_sdif0_cry[7] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[8] ARI1 FCI In - 1.006 - CoreResetP_0.count_sdif0_cry[8] ARI1 FCO Out 0.014 1.020 - count_sdif0_cry[8] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[9] ARI1 FCI In - 1.020 - CoreResetP_0.count_sdif0_cry[9] ARI1 FCO Out 0.014 1.034 - count_sdif0_cry[9] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[10] ARI1 FCI In - 1.034 - CoreResetP_0.count_sdif0_cry[10] ARI1 FCO Out 0.014 1.048 - count_sdif0_cry[10] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_cry[11] ARI1 FCI In - 1.048 - CoreResetP_0.count_sdif0_cry[11] ARI1 FCO Out 0.014 1.062 - count_sdif0_cry[11] Net - - 0.000 - 1 CoreResetP_0.count_sdif0_s[12] ARI1 FCI In - 1.062 - CoreResetP_0.count_sdif0_s[12] ARI1 S Out 0.063 1.126 - count_sdif0_s[12] Net - - 0.971 - 1 CoreResetP_0.count_sdif0[12] SLE D In - 2.097 - =============================================================================================== Total path delay (propagation time + setup) of 2.319 is 0.710(30.6%) logic and 1.609(69.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: pemgt|CORETSE_AHBi01_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBi1OII[2] pemgt|CORETSE_AHBi01_inferred_clock SLE Q CORETSE_AHBi1OII[2] 0.094 3.420 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBi1OII[4] pemgt|CORETSE_AHBi01_inferred_clock SLE Q CORETSE_AHBi1OII[4] 0.076 3.548 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBl0OII[4] pemgt|CORETSE_AHBi01_inferred_clock SLE Q CORETSE_AHBl0OII[4] 0.094 3.801 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBi1OII[0] pemgt|CORETSE_AHBi01_inferred_clock SLE Q CORETSE_AHBi1OII[0] 0.094 3.931 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBl0OII[0] pemgt|CORETSE_AHBi01_inferred_clock SLE Q CORETSE_AHBl0OII[0] 0.076 3.935 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBl0OII[1] pemgt|CORETSE_AHBi01_inferred_clock SLE Q CORETSE_AHBl0OII[1] 0.094 3.948 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBl0OII[3] pemgt|CORETSE_AHBi01_inferred_clock SLE Q CORETSE_AHBl0OII[3] 0.076 3.988 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBl0OII[2] pemgt|CORETSE_AHBi01_inferred_clock SLE Q CORETSE_AHBl0OII[2] 0.076 4.028 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBi1OII[1] pemgt|CORETSE_AHBi01_inferred_clock SLE Q CORETSE_AHBi1OII[1] 0.094 4.047 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBi1OII[3] pemgt|CORETSE_AHBi01_inferred_clock SLE Q CORETSE_AHBi1OII[3] 0.094 4.097 ======================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[8] pemgt|CORETSE_AHBi01_inferred_clock SLE D CORETSE_AHBiOIII[8] 9.778 3.420 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[6] pemgt|CORETSE_AHBi01_inferred_clock SLE D CORETSE_AHBiOIII[6] 9.778 3.507 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[13] pemgt|CORETSE_AHBi01_inferred_clock SLE D CORETSE_AHBiOIII[13] 9.778 3.931 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[11] pemgt|CORETSE_AHBi01_inferred_clock SLE D CORETSE_AHBiOIII[11] 9.778 3.958 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[15] pemgt|CORETSE_AHBi01_inferred_clock SLE D CORETSE_AHBiOIII[15] 9.778 4.372 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[3] pemgt|CORETSE_AHBi01_inferred_clock SLE D CORETSE_AHBiOIII[3] 9.778 4.399 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[10] pemgt|CORETSE_AHBi01_inferred_clock SLE D CORETSE_AHBiOIII[10] 9.778 4.399 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[1] pemgt|CORETSE_AHBi01_inferred_clock SLE D CORETSE_AHBiOIII[1] 9.778 4.465 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[5] pemgt|CORETSE_AHBi01_inferred_clock SLE D CORETSE_AHBiOIII[5] 9.778 4.492 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[4] pemgt|CORETSE_AHBi01_inferred_clock SLE D CORETSE_AHBiOIII[4] 9.778 4.492 =========================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 6.358 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.420 Number of logic level(s): 8 Starting point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBi1OII[2] / Q Ending point: CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[8] / D The start point is clocked by pemgt|CORETSE_AHBi01_inferred_clock [rising] on pin CLK The end point is clocked by pemgt|CORETSE_AHBi01_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBi1OII[2] SLE Q Out 0.094 0.094 - CORETSE_AHBi1OII[2] Net - - 0.745 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBo01_0_o2_1_0 CFG2 A In - 0.839 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBo01_0_o2_1_0 CFG2 Y Out 0.076 0.915 - CORETSE_AHBo01_0_o2_1_0 Net - - 0.590 - 3 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBo01_0_o2_1_0_RNIMPJP CFG3 C In - 1.505 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBo01_0_o2_1_0_RNIMPJP CFG3 Y Out 0.194 1.699 - CORETSE_m6_e_5 Net - - 0.548 - 2 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBo01_0_a2_4_0_RNIB8JV3 CFG4 D In - 2.247 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBo01_0_a2_4_0_RNIB8JV3 CFG4 Y Out 0.236 2.483 - N_1831 Net - - 0.749 - 11 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBiOIII_0_1_1[8] CFG4 D In - 3.231 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBiOIII_0_1_1[8] CFG4 Y Out 0.284 3.515 - CORETSE_AHBiOIII_0_1_1[8] Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBiOIII_0_1[8] CFG4 D In - 3.998 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBiOIII_0_1[8] CFG4 Y Out 0.276 4.274 - CORETSE_AHBiOIII_0_1[8] Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBiOIII_0_4[8] CFG4 C In - 4.758 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBiOIII_0_4[8] CFG4 Y Out 0.177 4.934 - CORETSE_AHBiOIII_0_4[8] Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBiOIII_0_6[8] CFG4 B In - 5.417 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBiOIII_0_6[8] CFG4 Y Out 0.143 5.560 - CORETSE_AHBiOIII_0_6[8] Net - - 0.483 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBiOIII_0[8] CFG4 C In - 6.044 - CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBiOIII_0[8] CFG4 Y Out 0.177 6.220 - CORETSE_AHBiOIII[8] Net - - 0.138 - 1 CORETSE_AHB_0.CoreTSE_top_inst.CORETSE_AHBio0\.CORETSE_AHBOi0.CORETSE_AHBIoi0.CORETSE_AHBI011.CORETSE_AHBOIIII[8] SLE D In - 6.358 - ============================================================================================================================================================================================= Total path delay (propagation time + setup) of 6.580 is 1.878(28.5%) logic and 4.702(71.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------- FCCC_1.CCC_INST System CCC LOCK FCCC_1_LOCK 0.000 7.906 FCCC_2.CCC_INST System CCC LOCK FCCC_2_LOCK 0.000 7.973 ===================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- FCCC_3.CCC_INST System CCC NGMUX0_ARST_N PHY_RST_c 10.000 7.906 FCCC_3.CCC_INST System CCC NGMUX1_ARST_N PHY_RST_c 10.000 7.906 ============================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 2.094 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 7.906 Number of logic level(s): 1 Starting point: FCCC_1.CCC_INST / LOCK Ending point: FCCC_3.CCC_INST / NGMUX0_ARST_N The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- FCCC_1.CCC_INST CCC LOCK Out 0.000 0.000 - FCCC_1_LOCK Net - - 0.971 - 1 AND2_0 AND2 B In - 0.971 - AND2_0 AND2 Y Out 0.143 1.114 - PHY_RST_c Net - - 0.980 - 3 FCCC_3.CCC_INST CCC NGMUX0_ARST_N In - 2.094 - ======================================================================================= Total path delay (propagation time + setup) of 2.094 is 0.143(6.8%) logic and 1.951(93.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] @W:MT447 : synthesis.fdc(20) | Timing constraint (from [get_cells { CoreResetP_0.MSS_HPMS_READY_int }] to [get_cells { CoreResetP_0.sm0_areset_n_rcosc CoreResetP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(21) | Timing constraint (from [get_cells { CoreResetP_0.MSS_HPMS_READY_int CoreResetP_0.SDIF*_PERST_N_re }] to [get_cells { CoreResetP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT443 : synthesis.fdc(23) | Timing constraint (through [get_nets { CoreConfigP_0.FIC_2_APB_M_PSEL CoreConfigP_0.FIC_2_APB_M_PENABLE }] to [get_cells { CoreConfigP_0.FIC_2_APB_M_PREADY* CoreConfigP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design Finished final timing analysis (Real Time elapsed 0h:01m:04s; CPU Time elapsed 0h:01m:04s; Memory used current: 247MB peak: 327MB) Finished timing report (Real Time elapsed 0h:01m:04s; CPU Time elapsed 0h:01m:04s; Memory used current: 247MB peak: 327MB) --------------------------------------- Resource Usage Report for CoreTSE_Webserver Mapping to part: m2s090tsfbga484-1 Cell usage: AND2 1 use CCC 4 uses CLKINT 27 uses MSS_075 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_075 1 use SYSRESET 1 use CFG1 22 uses CFG2 1353 uses CFG3 1788 uses CFG4 5163 uses Carry primitives used for arithmetic functions: ARI1 1456 uses Sequential Cells: SLE 5172 uses DSP Blocks: 0 I/O ports: 41 I/O primitives: 23 BIBUF 5 uses INBUF 4 uses INBUF_DIFF 1 use OUTBUF 10 uses TRIBUFF 3 uses Global Clock Buffers: 27 RAM/ROM usage summary Block Rams (RAM1K18) : 14 Total LUTs: 9782 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 504; LUTs = 504; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 5172 + 0 + 504 + 0 = 5676; Total number of LUTs after P&R: 9782 + 0 + 504 + 0 = 10286; Mapper successful! At Mapper Exit (Real Time elapsed 0h:01m:04s; CPU Time elapsed 0h:01m:04s; Memory used current: 80MB peak: 327MB) Process took 0h:01m:04s realtime, 0h:01m:04s cputime # Thu Nov 17 15:27:54 2016 ###########################################################]